Power Control

1. System Overview

The rear master power switch controls whether the internal power supply is energized. When the rear switch is on, the supply provides raw +5 V and +12 V continuously. The power-control PCB is powered directly from the raw +5 V rail, so it remains active even while the rest of the computer is off.

The motherboard does not receive either rail until the power-control circuit energizes a DPST relay. One relay contact switches +5 V and the other switches +12 V. Ground remains connected continuously and is not switched.

                INTERNAL POWER SUPPLY

              +5V_RAW            +12V_RAW
                 |                  |
                 |                  |
                 |             +----+----+
                 |             | relay   |
                 |             | contact |
                 |             +----+----+
                 |                  |
            +----+----+             +-------------> +12V_SW
            |         |
            | control |
            | circuit |
            |         |
            +----+----+
                 |
                 | controls relay
                 |
              +--+-----+
              | relay  |
              | driver |
              +--+-----+
                 |
              relay coil

        +5V_RAW ---- relay contact ----------------> +5V_SW

        GND ---------------------------------------> GND
        

The raw rails are the outputs directly from the internal power supply. The switched rails are the outputs from the relay and are the only +5 V and +12 V rails delivered to the motherboard.

2. Power Path

The power-control PCB has one low-voltage power input from the internal supply and one low-voltage switched output to the computer. The board receives +5V_RAW, +12V_RAW, and GND. It produces +5V_SW, +12V_SW, and GND.

The relay must provide two independent normally-open contacts. Each contact is used for one positive supply rail. The relay contacts must be rated for at least 10 A at 12 VDC. Board bring-up must verify that contact heating and the startup current of each switched rail remain within the selected relay's DC ratings.

3. Front-Panel Interface

The front panel contains only the momentary power button and the power LED. Both devices connect to the power-control PCB with low-current wiring.

The power button is a normally-open momentary switch. It does not carry either main power rail and does not drive the relay directly. The switch is interpreted entirely by the logic circuit.

The power LED is controlled by the stored logical power state. It lights when the relay is commanded on and turns off when the relay is commanded off.

        FRONT PANEL                         POWER-CONTROL PCB

        +--------------+                  +----------------------+
        | momentary    |------------------| button input         |
        | power button |------------------| ground               |
        +--------------+                  |                      |
                                          |                      |
        +--------------+                  |                      |
        | power LED    |------------------| LED drive            |
        |              |------------------| ground               |
        +--------------+                  +----------------------+
        

4. Button Conditioning

The button input is pulled to a defined logic level when the switch is open. A small RC network suppresses contact bounce, and one gate in U_POWER_SCHMITT, an SN74HC14N, converts the filtered signal into a clean digital button signal.

A 100 kohm pull-up resistor and 100 nF capacitor provide a nominal 10 ms time constant before the Schmitt trigger. A 1 kohm resistor in the switch lead limits capacitor discharge current when the contacts close.

The specified switch is the C&K FP11SPC1B1TP00, a normally-open momentary SPST pushbutton. The same part is used for the manual reset switch in clock-and-reset.html and the NMI button in interrupts.html.

The conditioned internal signal is named BTN. BTN is high while the button is pressed and low while it is released.

        button released -> BTN = 0
        button pressed  -> BTN = 1
        

Releasing the button immediately cancels any incomplete power-on or power-off timing sequence and resets the hold-time counter.

5. Timing and State Logic

The control logic consists of a slow clock source, a four-bit hold counter, a selectable threshold comparator, a power-state flip-flop, and a lockout flip-flop.

74HC4060 Hold-Time Clock

U_HOLD_OSC, an SN74HC4060N, provides the RC oscillator and binary divider. Its oscillator uses a 13.7 kohm resistor, a 137 kohm resistor, and a 1 nF C0G or NP0 capacitor in the manufacturer's two-resistor network. The datasheet's simplified equation gives a nominal oscillator frequency of 33.2 kHz.

fOSC = 0.455 / (13.7 kohm * 1 nF) = 33.2 kHz

Output QN is the divide-by-16384 output, so its full period is nominally 493 ms. Resistor, capacitor, threshold, temperature, and device tolerances set the actual period. Measure the resulting delays during board acceptance.

One U_POWER_SCHMITT stage inverts QN to make HOLD_CLK. The hold counter advances on each rising edge of HOLD_CLK, once per full QN period. The inversion delays the first count until QN completes its first full period instead of counting on its first rising edge.

74HC161 Hold Counter

U_HOLD_COUNT, an SN74HC161N four-bit binary counter, measures how long the front-panel button remains continuously pressed. Its two enable inputs and active-low load input are tied high. HOLD_CLK drives its clock, and TIMER_ENABLE drives its active-low clear input. The counter advances at a nominal 2.03 counts per second.

tON  = (6 + 0.5) * 493 ms = 3.21 seconds
tOFF = (10 + 0.5) * 493 ms = 5.18 seconds

If the button is released before the selected target count is reached, the counter returns to zero and no power-state change occurs.

74HC85 Threshold Selection

U_HOLD_COMPARE, a CD74HC85E four-bit magnitude comparator, compares the current hold count against a target selected by the current power state.

The count connects to comparator input A. The target connects to input B as B3 = POWER_STATE, B2 = POWER_STATE_n, B1 = 1, and B0 = 0. The cascade inputs are fixed for a single comparator: A=B is high, while A>B and A<B are low.

        power state = OFF -> target = 0110 binary = 6
        power state = ON  -> target = 1010 binary = 10
        

The comparator's A=B output is HOLD_DONE. It does not drive a clock input directly. One SN74HC08N gate combines it with QN to make STATE_CLK. The counter changes while QN is low, which masks comparator skew. Half a timer cycle later, the rising edge of QN clocks the state flip-flops if the comparison has settled equal.

STATE_CLK = QN AND HOLD_DONE

Changing POWER_STATE selects the other target, and setting DONE resets the timer. Both actions remove the equality condition and return STATE_CLK low after one edge.

74HC74 Power-State Flip-Flop

One half of U_POWER_STATE, an SN74HC74N, stores the logical power state. Its inverted output feeds its D input, and STATE_CLK drives its positive-edge clock. Its preset input is tied high. POR_OK drives its active-low clear input, so the stored state is off during power-on reset.

        OFF + 3-second hold -> ON
        ON  + 5-second hold -> OFF
        

The stored state is named POWER_STATE. It controls the relay driver and front-panel power LED.

74HC74 Button-Release Lockout

The second half of U_POWER_STATE stores DONE. Its D and preset inputs are tied high, and STATE_CLK drives its positive-edge clock. Its active-low clear input receives DONE_CLEAR_n, so a completed hold sets DONE until the button is released.

While DONE is set, the timer is disabled and reset. This prevents one very long button hold from repeatedly turning the computer on and off. Releasing the button clears DONE and arms the circuit for the next press.

        button pressed
             |
             v
        required hold time reached
             |
             v
        power state changes
             |
             v
        DONE = 1
             |
             v
        timer disabled until button release
        

74HC08 Enable Logic

U_POWER_GATE, an SN74HC08N, combines the button, lockout, and reset signals. Two gates form TIMER_ENABLE, a third forms DONE_CLEAR_n, and the fourth forms STATE_CLK.

        TIMER_ENABLE = BTN AND DONE_n AND POR_OK
        DONE_CLEAR_n = BTN AND POR_OK
        STATE_CLK    = QN AND HOLD_DONE
        

TIMER_ENABLE connects directly to the hold counter's active-low clear input. Another U_POWER_SCHMITT stage inverts it for the oscillator's active-high clear input. Both devices stay at zero until a new button press is accepted.

6. Internal Signal Reference

Signal names ending in _n are active low. Raw and switched rail names describe separate power nets and do not use the active-low suffix.

7. Relay Control

The 74HC logic does not drive the relay coil directly. A discrete transistor provides the coil current. The design uses a 12 V relay coil because the raw +12 V rail is present on the PCB while the computer is off.

The specified part is the Omron G4W-2212P-US-TV5-HP DC12, a two-pole normally-open power relay with a 12 V DC coil.

A 2N7000 N-channel MOSFET drives the selected relay coil. The coil current must remain within the MOSFET's drain-current and dissipation limits at a 5 V gate drive. POWER_STATE drives the gate through 100 ohms, and a 100 kohm gate-to-ground resistor keeps the relay off while the logic supply rises.

A 1N4001 flyback diode connects across the relay coil, with its cathode at +12V_RAW and anode at the MOSFET drain. It conducts the coil current when the MOSFET turns off.

        +12V_RAW
            |
         relay coil
            |
            +---- flyback diode ----+
            |                       |
         transistor                 |
            |                       |
           GND ---------------------+

        POWER_STATE -> transistor control
        

The relay uses two normally-open contacts. One switches +5V_RAW to +5V_SW. The other switches +12V_RAW to +12V_SW. Ground is never switched.

        +5V_RAW  ---- normally-open contact ---- +5V_SW
        +12V_RAW ---- normally-open contact ---- +12V_SW
        GND      ------------------------------- GND
        

The relay contact rating must be based on DC current, not only an AC contact rating. The selected relay should also tolerate the charging current of the motherboard and expansion-card bypass and bulk capacitors when the contacts close.

8. Power-On Reset

The control logic includes its own power-on-reset circuit so that enabling the rear master switch always starts from a defined state. The default state is computer off, relay released, and hold timer reset.

A 100 kohm pull-up and 1 uF capacitor to ground feed two U_POWER_SCHMITT stages. The second stage produces POR_OK, which stays low while the RC node crosses the first stage's upper threshold. A 1N4148 diode across the resistor, with its anode at the RC node and cathode at +5V_RAW, discharges the capacitor when raw power falls. This restores the reset delay after a short power interruption.

During reset, the power-state flip-flop is forced off and the button-release lockout is cleared. The relay therefore cannot energize accidentally during power-up.

        rear master switch turned on
                  |
                  v
             +5V_RAW rises
                  |
                  v
           power-on reset active
                  |
                  v
        POWER_STATE = OFF
        DONE = 0
        counter = 0
        relay = released
                  |
                  v
              POR_OK = 1
                  |
                  v
        front button becomes active
        

9. Power LED

The front-panel power LED follows POWER_STATE. The LED and its two wires run between the front panel and the power-control PCB.

A red LED and 1 kohm series resistor connect from POWER_STATE to ground. The LED current is about 3 mA with a 2 V forward drop, within the SN74HC74N's 4 mA output specification at a 5 V supply. The specified LED is the Kingbright WP7113ID, a 5 mm red indicator.

        POWER_STATE = 0 -> LED off
        POWER_STATE = 1 -> LED on
        

10. Component Summary

The control circuit uses through-hole 74HC logic and discrete parts available within the project's pre-1993 component limit.

Passive Components

11. Operating Sequence

Rear Master Switch Off

The internal power supply is not energized. The control PCB, motherboard, relay, and front-panel LED are all off.

Rear Master Switch On, Computer Off

The internal power supply provides raw +5 V and +12 V. The control PCB operates from +5V_RAW, but the relay remains released. The motherboard receives neither switched positive rail.

Short Press While Off

Pressing the front button for less than approximately three seconds starts the timer but does not change the power state. Releasing the button resets the timer to zero.

Three-Second Hold While Off

When the hold counter reaches six counts, the comparator matches. The next rising edge of QN changes POWER_STATE to on, energizes the relay, connects both switched rails to the motherboard, and lights the power LED.

Short Press While On

Pressing the front button for less than approximately five seconds starts the timer but does not change the power state. Releasing the button resets the timer to zero.

Five-Second Hold While On

When the hold counter reaches ten counts, the comparator matches. The next rising edge of QN changes POWER_STATE to off, releases the relay, disconnects both switched rails from the motherboard, and turns off the power LED.

Continued Button Hold After an Action

The DONE latch disables the timer immediately after a successful power-state change. Keeping the button held cannot cause a second state change. The user must release the button before another timed press can begin.

12. Board Layout and Acceptance

Power the control PCB from +5V_RAW, not the switched +5 V rail. The logic must remain active while the computer is off so it can detect the next button press.

The +12 V relay coil is also connected to the raw side of the power system. This is required because the relay must be able to energize before +12V_SW exists.

Ground remains continuous at all times. Switching ground would create unnecessary problems with cable shields, external interfaces, peripherals, and alternate return paths.

Every unused CMOS logic input must be tied to a defined high or low level. Unused inputs must not be left floating.

The power-control circuit handles only the low-voltage outputs of the internal power supply. The rear master switch and AC input belong to the separate mains-power portion of the computer and are outside the scope of this control-circuit document.

Keep both switched-current paths short and wide, and keep them away from the button, oscillator, and comparator traces. Place the 1N4001 at the relay coil, the 2N7000 gate pull-down at the transistor, and each 100 nF bypass capacitor at its logic package. Join control ground to the power-return path without routing relay-coil current through the logic ground traces.

The assembled board must pass these checks before release:

• A short press in either power state leaves the relay and LED unchanged.
• A continuous press changes the state once at the applicable nominal delay, and holding the button does not cause another change.
• Releasing the button resets the timer and arms the next press.
• Turning the rear switch on, including after a short interruption, starts with the relay released and LED off.
• At 5 A on +5V_SW and 3 A on +12V_SW, relay contact drop, connector heating, trace heating, MOSFET temperature, and relay-coil current remain within their component ratings.
• Closing and opening the relay does not retrigger the state logic or produce relay chatter.

13. Sources

• Texas Instruments, SN74HC4060, RC-oscillator connection, frequency equation, divider outputs, and active-high clear behavior.
• Texas Instruments, SN74HC161, positive-edge counting, count enables, and asynchronous active-low clear behavior.
• Texas Instruments, CD74HC85, four-bit magnitude comparison and single-comparator cascade inputs.
• Texas Instruments, SN74HC74, power-state and button-release storage, asynchronous clear, and output-current limits.
• Texas Instruments, SN74HC08, timer-enable and clear gating.
• Texas Instruments, SN74HC14, button conditioning, oscillator inversion, and power-on-reset conditioning.