Debug Display

1. Input

The display receives DEBUG_Q7..DEBUG_Q0 from U_DEBUG. The latch and qualified write timing are defined in Bus and Decode. The debug register is described in System Control.

Each nibble displays one hexadecimal digit. The glyph set includes 0 through 9 and A through F.

2. Decoder Selection

Two ATF16V8BQL-15PU programmable logic devices implement the hexadecimal decoders. U_HEX_LEFT handles the upper nibble. U_HEX_RIGHT handles the lower nibble. Both devices use the same programmed logic image.

The decoder is static. It does not multiplex the displays and does not require a scan clock. Each GAL produces seven active-low segment outputs. The outputs directly sink the display segment current.

The display is the one place on the board where an SPLD replaces discrete 74-series decode gates: sixteen glyphs across seven segments costs far more gates than it saves. The system-register decode, write qualification, and the U_DEBUG latch are all discrete logic, described in Bus and Address Decode.

DEBUG_Q7..DEBUG_Q4 -> U_HEX_LEFT  -> seven 680 ohm resistors -> left digit
DEBUG_Q3..DEBUG_Q0 -> U_HEX_RIGHT -> seven 680 ohm resistors -> right digit

3. Display and Segment Naming

DS_DEBUG_LEFT and DS_DEBUG_RIGHT are Kingbright SA56-11EWA 0.56 inch high-efficiency red common-anode displays. Both common-anode pins connect to +5 V. The decimal point is unused.

  -- a --
 |       |
 f       b
 |       |
  -- g --
 |       |
 e       c
 |       |
  -- d --

Segment outputs use the names SEG_A_n through SEG_G_n. A low output lights the corresponding segment.

4. Hexadecimal Truth Table

Lowercase-looking b and d distinguish the seven-segment forms from 8 and 0.

5. GAL Logic

The GALs operate in simple combinational mode. The equations below list the nibble values for which each active-low segment output is high, which means that segment is off.

SEG_A_n = 1 for 1, 4, B, D
SEG_B_n = 1 for 5, 6, B, C, E, F
SEG_C_n = 1 for 2, C, E, F
SEG_D_n = 1 for 1, 4, 7, A, F
SEG_E_n = 1 for 1, 3, 4, 5, 7, 9
SEG_F_n = 1 for 1, 2, 3, 7, D
SEG_G_n = 1 for 0, 1, 7, C

The widest output, SEG_E_n, needs six canonical product terms. Simple mode gives every output eight, so no minimization is required to fit. Seven of the eight macrocells drive segments; the eighth is pin 19, described below.

The pin and equation body in CUPL form follows. Add the standard header and DEVICE g16v8; to compile it to the JEDEC image used for both devices. Every output is combinational and none needs output-enable control, so the fitter selects simple mode, in which pins 15 and 16 are permanently enabled outputs. N0 is the least significant nibble bit. Each output is the sum of the minterms that switch its segment off; every other nibble value lights the segment. The listing is canonical, so the fitter minimizes it before programming.

PIN  2 = N0 ;   PIN  3 = N1 ;   PIN  4 = N2 ;   PIN  5 = N3 ;

PIN 18 = SEG_A_n ;
PIN 17 = SEG_B_n ;
PIN 16 = SEG_C_n ;
PIN 15 = SEG_D_n ;
PIN 14 = SEG_E_n ;
PIN 13 = SEG_F_n ;
PIN 12 = SEG_G_n ;
PIN 19 = SPARE ;

SEG_A_n = (!N3 & !N2 & !N1 &  N0)    /* 1 */
        # (!N3 &  N2 & !N1 & !N0)    /* 4 */
        # ( N3 & !N2 &  N1 &  N0)    /* B */
        # ( N3 &  N2 & !N1 &  N0) ;  /* D */

SEG_B_n = (!N3 &  N2 & !N1 &  N0)    /* 5 */
        # (!N3 &  N2 &  N1 & !N0)    /* 6 */
        # ( N3 & !N2 &  N1 &  N0)    /* B */
        # ( N3 &  N2 & !N1 & !N0)    /* C */
        # ( N3 &  N2 &  N1 & !N0)    /* E */
        # ( N3 &  N2 &  N1 &  N0) ;  /* F */

SEG_C_n = (!N3 & !N2 &  N1 & !N0)    /* 2 */
        # ( N3 &  N2 & !N1 & !N0)    /* C */
        # ( N3 &  N2 &  N1 & !N0)    /* E */
        # ( N3 &  N2 &  N1 &  N0) ;  /* F */

SEG_D_n = (!N3 & !N2 & !N1 &  N0)    /* 1 */
        # (!N3 &  N2 & !N1 & !N0)    /* 4 */
        # (!N3 &  N2 &  N1 &  N0)    /* 7 */
        # ( N3 & !N2 &  N1 & !N0)    /* A */
        # ( N3 &  N2 &  N1 &  N0) ;  /* F */

SEG_E_n = (!N3 & !N2 & !N1 &  N0)    /* 1 */
        # (!N3 & !N2 &  N1 &  N0)    /* 3 */
        # (!N3 &  N2 & !N1 & !N0)    /* 4 */
        # (!N3 &  N2 & !N1 &  N0)    /* 5 */
        # (!N3 &  N2 &  N1 &  N0)    /* 7 */
        # ( N3 & !N2 & !N1 &  N0) ;  /* 9 */

SEG_F_n = (!N3 & !N2 & !N1 &  N0)    /* 1 */
        # (!N3 & !N2 &  N1 & !N0)    /* 2 */
        # (!N3 & !N2 &  N1 &  N0)    /* 3 */
        # (!N3 &  N2 &  N1 &  N0)    /* 7 */
        # ( N3 &  N2 & !N1 &  N0) ;  /* D */

SEG_G_n = (!N3 & !N2 & !N1 & !N0)    /* 0 */
        # (!N3 & !N2 & !N1 &  N0)    /* 1 */
        # (!N3 &  N2 &  N1 &  N0)    /* 7 */
        # ( N3 &  N2 & !N1 & !N0) ;  /* C */

SPARE = 'b'1 ;

Pins 1 and 11 are tied low and unused. SPARE on pin 19 is a constant-high output left unconnected.

6. GAL Connections

The table applies to both U_HEX_LEFT and U_HEX_RIGHT. Pins 2 through 5 carry the local nibble. Unused dedicated inputs are tied low. Pin 19 is left unconnected and is programmed as a constant-high unused output.

7. Display Connections

One 680 ohm resistor is placed in series with each segment cathode. The same connection table applies to both displays.

8. Segment Current

The motherboard supply is 5 V +/-5%, or 4.75 V to 5.25 V. The SA56-11EWA data sheet gives a typical segment forward voltage of 1.9 V and a maximum of 2.3 V at 10 mA. The ATF16V8BQL data sheet guarantees VOL <= 0.5 V at IOL = 24 mA with minimum VCC.

R_seg = (VCC - Vf_segment - VOL) / I_segment

Using R_seg = 680 ohm:

I_segment = (5.00 V - 1.90 V - 0.50 V) / 680 ohm
          = 3.82 mA

A low-supply, high-forward-voltage calculation gives:

I_segment = (4.75 V - 2.30 V - 0.50 V) / 680 ohm
          = 2.87 mA

The display data sheet does not specify a minimum forward voltage. A precise worst-case maximum LED current cannot be calculated from that data. A resistor-only upper bound can still be calculated by assuming zero LED and driver voltage drop. With a 1% low 680 ohm resistor:

R_min = 680 ohm * 0.99
      = 673.2 ohm

I_segment < 5.25 V / 673.2 ohm
          < 7.80 mA

This bound remains below the GAL output test current of 24 mA. The expected operating current is about 3 to 4 mA per lit segment. Brightness remains an assembled-board check because the display data sheet specifies luminous intensity at 10 mA.

Displaying 88 lights all fourteen segments. At the nominal calculation above, the LED load is about 53.5 mA.

I_88 = 14 * 3.82 mA
     = 53.5 mA

The resistor-only upper bound for all fourteen segments is 109.2 mA. The ATF16V8BQL-15 standby supply current is 15 mA maximum per device with the outputs open. Reserving both GAL supply-current maxima plus the resistor-only LED-current bound gives a conservative debug-display +5 V allocation below 139.2 mA.

The GAL data sheet specifies individual output loading but does not provide a separate guaranteed simultaneous package-wide sink-current rating for this use. Confirm the 88 condition on the assembled board and check device temperature and the +5 V rail.

9. Reset and Power-On Behavior

No display blanking is fitted. U_DEBUG has no reset and its stored value is indeterminate at power-on. The GALs decode that value immediately, so the two displays show an indeterminate hexadecimal value until firmware writes $E80003.

Reset-only blanking would hide the value only while reset is asserted. It would not initialize U_DEBUG. The design therefore leaves the display active and requires firmware to write a known debug value during initialization.

10. Fanout

Each DEBUG_Qx output drives one ATF16V8BQL input and an optional passive test pad. No display signal is shared between the two GALs.

The static input current is well below the SN74HCT574 output rating. No buffer is required. PCB routing and a passive test pad add capacitance but do not create a DC fanout problem.

11. Timing

The ATF16V8BQL-15 input-to-combinational-output propagation delay is 15 ns maximum. A debug-register write can change several latch outputs at once, so an intermediate segment pattern may exist while the GAL settles. The transition is too short to be visible and does not affect the stored value.

The display has no refresh oscillator and no periodic switching after the debug byte becomes stable.

12. Decoupling and Placement

Place one 100 nF capacitor and one 1 uF capacitor in parallel between VCC and GND at U_HEX_LEFT. Place another 100 nF and 1 uF pair at U_HEX_RIGHT. Keep each pair close to the package.

Place DS_DEBUG_LEFT and DS_DEBUG_RIGHT next to each other at a visible motherboard edge. Place the upper-nibble digit on the left. Mark the pair DEBUG HI LO on the silkscreen.

13. Parts Added

14. Assembled-System Acceptance

1. Program U_HEX_LEFT and U_HEX_RIGHT with the same verified JEDEC image.
2. Write $5A to $E80003. Confirm that the display reads 5A.
3. Write $00 through $0F. Confirm the right digit walks through 0 1 2 3 4 5 6 7 8 9 A b C d E F.
4. Write $00, $10, through $F0. Confirm the left digit walks through the same glyph set.
5. Hold $88. Confirm all fourteen segments light, neither GAL becomes noticeably warm, and the local +5 V rail remains within specification.
6. Confirm both digits remain steady after a write and show no visible flicker.

15. Sources

GAL pinout, 5 V +/-10% operating range, input leakage, pin capacitance, 15 ns propagation delay, 15 mA maximum BQL standby current, and the VOL test point come from the Microchip ATF16V8B, ATF16V8BQ, and ATF16V8BQL data sheet, document Atmel-0364K.

Display polarity, pinout, 1.9 V typical forward voltage, 2.3 V maximum forward voltage at 10 mA, and 30 mA DC forward-current rating come from the Kingbright SA56-11EWA data sheet, specification DSAP8372 / 1301000536.

The SN74HCT574 +/-6 mA output-drive figure comes from the Texas Instruments SN54HCT574, SN74HCT574 data sheet, SCLS177H.