Bus and Address Decode

1. Purpose

The address decoder determines which motherboard device owns each CPU bus cycle. The decoder implements the frozen memory map without transferring data itself.

2. Design Rules

• The motherboard uses a 16-bit external bus.
• 8-bit peripherals connect to D7..D0 and use /LDS.
• The CL-GD5428 uses a 16-bit interface with swapped byte lanes.
• A leading slash in this document, or an _n suffix in a signal name, marks an active-low signal.
• Any address or register change requires a new memory map revision.
• Normal memory and I/O devices must not respond to CPU-space cycles.
• Address decoding uses discrete 74-series logic.
• The processor and motherboard logic run at +5 V.
• The processor clock is 10 MHz.
• The computer does not support DMA or bus arbitration.
• RESET_n is the external reset-source signal, not the processor's bidirectional /RESET pin.
• Peripheral documents define register-level decoding and adapter timing. This document defines the motherboard selects and response contract presented to those adapters.

3. CPU Bus Signals

The address decoder uses a subset of the MC68EC000 bus signals to determine the address being accessed, the type of bus cycle, the data width of the transfer, and when the transfer is active.

4. Bus Arbitration

This computer has one bus master. DMA and external bus arbitration are not supported.

5. Simplified Bus Cycle

The MC68EC000 uses an asynchronous bus. A transfer begins when the CPU places an address and control information on the bus, then asserts /AS. The selected device or motherboard asserts /DTACK when the data has been provided or accepted.

Read Cycle

1. The CPU places the address and function code on their buses.
2. The CPU sets R/W high to indicate a read.
3. The CPU asserts /AS to indicate that the address is valid.
4. The CPU asserts /UDS, /LDS, or both, depending on which byte lanes are being accessed.
5. The address decoder selects the target device.
6. The selected device drives the requested data onto the data bus.
7. The selected device or motherboard asserts /DTACK.
8. The CPU latches the data and completes the bus cycle.
9. The CPU releases /AS and the data strobes, and the selected device stops driving the data bus.

Write Cycle

1. The CPU places the address and function code on their buses.
2. The CPU sets R/W low to indicate a write.
3. The CPU asserts /AS to indicate that the address is valid.
4. The CPU drives the value being written onto the data bus.
5. The CPU asserts /UDS, /LDS, or both, depending on which byte lanes are being written.
6. The address decoder selects the target device.
7. The selected device accepts the data.
8. The selected device or motherboard asserts /DTACK.
9. The CPU completes the bus cycle and releases the bus strobes.

This is a logical description of a transfer. Section 24 covers the timing of the shared decoder. Each device page covers the timing between its request input and completion output.

6. CPU Space Detection

The processor function-code outputs identify the address space used by the current bus cycle. CPU space is selected when FC2, FC1, and FC0 are all high. The motherboard decodes this combination as the active-high internal signal CPU_SPACE (MC68000UM, p. 3-9).

CPU_SPACE = FC2 AND FC1 AND FC0

Implementation

Two gates in U_AND, an SN74HCT08N, implement the three-input function. A third gate in the same package generates ROM_CYCLE_n later in the decode chain.

CPU_SPACE_STAGE1 = FC2 AND FC1
CPU_SPACE        = CPU_SPACE_STAGE1 AND FC0

Gate 4, pins 12 and 13 in and pin 11 out, combines the two bus-error sources as BERR_n = TIMEOUT_BERR_n AND INT_BERR_n; see Bus Error and Timeout. Pin 7 connects to ground and pin 14 connects to +5 V. A 100 nF capacitor and a 1 uF capacitor are placed in parallel between pins 14 and 7 near the package.

CPU_SPACE prevents ordinary memory and I/O devices from responding to CPU-space cycles such as interrupt acknowledge cycles.

7. Normal Bus-Cycle Qualification

Ordinary memory and I/O devices respond only during an active, non-CPU-space bus cycle. The motherboard identifies that condition with the active-low internal signal NORMAL_CYCLE_n. In the equation below, AS_n is the motherboard name for the processor's /AS pin.

NORMAL_CYCLE_n = AS_n OR CPU_SPACE

Normal-Cycle Distribution

U_NORMAL_BUF, an SN74HCT244N, prevents the normal-cycle gate from driving every request gate directly. Three noninverting outputs distribute identical copies of the qualifier.

NORMAL_MEM_n = NORMAL_CYCLE_n
NORMAL_EXP_n = NORMAL_CYCLE_n
NORMAL_MISC_n = NORMAL_CYCLE_n

NORMAL_MEM_n drives the RAM, CL-GD5428, and top-I/O request gates. NORMAL_EXP_n drives the four expansion memory request gates. NORMAL_MISC_n drives the ROM-alias qualifier and timeout reset. No buffer output drives more than four HCT inputs.

8. Primary Address Decoder

The primary address decoder divides the processor's 16 MiB address space into eight regions of 2 MiB each. CPU address lines A23..A21 select one region through an SN74HCT138N 3-line-to-8-line decoder/demultiplexer with active-low outputs.

Address Bit Selection

A 2 MiB region contains 2^21 byte addresses. Address bits below A21 vary within a region, while A23..A21 identify which of the eight regions is selected.

Enable Inputs

The primary decoder remains enabled continuously. Its outputs describe the address currently present on the CPU address bus and are not themselves qualified by /AS. This configuration matches the enable conditions in SN74HCT138 table 7-1.

Region Decode

Physical Connections

A 100 nF capacitor and a 1 uF capacitor are placed in parallel between VCC and GND near U_PRIMARY. The SN74HCT138 datasheet recommends 100 nF and notes that 100 nF and 1 uF are commonly used in parallel.

The region outputs are raw address-decode signals. A region output being active does not by itself indicate that a CPU bus cycle is in progress. Device-specific requests combine these outputs with bus-cycle qualification, as shown below.

9. Qualified Region Requests

An OR gate combines a raw region-select signal with the appropriate buffered normal-cycle qualifier. The request goes low only when the address is in the selected region and a normal bus cycle is active.

DRAM Bank 1 Request

DRAM bank 1 occupies $200000-$3FFFFF, which corresponds to REGION1_n. The DRAM controller receives a bank 1 request when that region is selected during a normal bus cycle.

RAM1_REQ_n = REGION1_n OR NORMAL_MEM_n

RAM1_REQ_n goes to the DRAM controller, which generates the required timing for the DRAM /RAS input.

CL-GD5428 VGA Host-Memory Request

The CL-GD5428 VGA host-memory window occupies $800000-$9FFFFF, corresponding to REGION4_n.

The CL-GD5428 expects little-endian byte ordering, while the MC68EC000 uses big-endian byte ordering. The host interface connects CPU D15..D8 to CL-GD5428 D7..D0 and CPU D7..D0 to CL-GD5428 D15..D8. The matching byte-enable connections are swapped with the data lanes. This wiring also applies to the controller's I/O-register interface.

VGA_MEM_n = REGION4_n OR NORMAL_MEM_n

VGA_MEM_n is the motherboard-level CL-GD5428 VGA memory-window select. The CL-GD5428 host interface may decode the address further if needed.

Expansion Memory Requests

The decoder produces four qualified 2 MiB expansion-region requests. EXP_MEM2_n goes to front slot 1 and EXP_MEM3_n goes to front slot 2. EXP_MEM5_n and EXP_MEM6_n remain on the motherboard and have no connector destination.

EXP_MEM2_n = REGION2_n OR NORMAL_EXP_n
EXP_MEM3_n = REGION3_n OR NORMAL_EXP_n
EXP_MEM5_n = REGION5_n OR NORMAL_EXP_n
EXP_MEM6_n = REGION6_n OR NORMAL_EXP_n

10. Top I/O Slot Decoder

The top 2 MiB region, $E00000-$FFFFFF, contains the motherboard's I/O devices and firmware. This region is divided into sixteen slots of 128 KiB each.

Top I/O Cycle Qualification

An OR gate combines the raw REGION7_n address decode with NORMAL_MEM_n. The resulting TOP_IO_n signal goes low only during a normal bus cycle in region 7.

TOP_IO_n = REGION7_n OR NORMAL_MEM_n

Slot Address Bits

Each I/O slot is 128 KiB, or 2^17 byte addresses. Address lines A20..A17 select one of the sixteen slots; lower address lines do not affect slot selection. In 16-bit mode, A0 remains high and /UDS and /LDS select the byte lane.

Address line A20 selects the group: low for slots 0 through 7 and high for slots 8 through 15. Address lines A19..A17 select one slot within that group.

Low-Half Decoder

U_IO_LOW is an SN74HCT138N that generates IO0_n through IO7_n.

U_IO_LOW is enabled only when TOP_IO_n is low and A20 is low.

High-Half Decoder

U_IO_HIGH is a second SN74HCT138N that generates IO8_n through IO15_n.

U_IO_HIGH is enabled only when TOP_IO_n is low and A20 is high.

IO9_n..IO14_n remain on the motherboard and have no connector destination under memory-map revision 1.0.

Each decoder has a 100 nF capacitor and a 1 uF capacitor in parallel between VCC and GND, placed near the IC.

11. System Register Decoder

I/O slot 4, covering $E80000-$E9FFFF, contains motherboard control and status registers.

U_SYSREG, an SN74HCT138N, decodes eight lower-byte registers. CPU address lines A3..A1 select the register number.

Register Address Selection

The motherboard's 8-bit registers use the lower data byte, D7..D0, and are accessed using /LDS. Consecutive registers are therefore located two CPU byte addresses apart. In the tables below, LDS_n is the motherboard name for the processor's /LDS pin.

Decoder Connections

Register Assignments

Address Mirroring

Within I/O slot 4, the local decoder ignores address lines A16..A4. The eight registers repeat every 16 bytes throughout the 128 KiB slot. Software uses only the eight canonical odd addresses from $E80001 through $E8000F.

U_SYSREG has a 100 nF capacitor and a 1 uF capacitor in parallel between VCC and GND, placed near the IC.

12. System Register Write Qualification

The system-register decoder identifies the selected register. An OR gate combines its active-low output with the MC68EC000 R/W signal to produce an active-low write qualifier. R/W is high during a read and low during a write.

Boot Overlay Register Write

SYSREG0 / SYSCTRL controls the boot ROM overlay. A write to this register generates OVERLAY_WRITE_n.

OVERLAY_WRITE_n = SYSREG0_n OR R/W

Debug Register Write

SYSREG1 / DEBUG is the write-only 8-bit hexadecimal debug display register. A write to this register generates DEBUG_WRITE_n.

DEBUG_WRITE_n = SYSREG1_n OR R/W

A spare inverter produces the positive edge required by the debug register. The edge occurs when the fully decoded write becomes active, while the CPU is still driving the data bus.

DEBUG_CLK = NOT DEBUG_WRITE_n

Write Qualification Truth Table

The SYSREGx_n signals already include bus-cycle qualification through IO4_n. The write equations do not need another /AS term.

System-Register Acknowledgement

Every lower-byte write in I/O slot 4 is acknowledged. Writes to SYSREG2..SYSREG7 are ignored. Reads and upper-byte-only accesses receive no system-register acknowledgement and reach the bus timeout.

SYSREG_ACK_STAGE_n = IO4_n OR LDS_n
SYSREG_DTACK_n     = SYSREG_ACK_STAGE_n OR R/W

Debug Byte Storage

U_DEBUG, an SN74HCT574N, stores the debug byte. Its data inputs connect to CPU D7..D0, its clock connects to DEBUG_CLK, and its active-low output enable connects to ground. The rising edge at the start of the qualified write stores the byte. The outputs feed the hexadecimal seven-segment decoder described in the debug display document.

13. Low 128 KiB Address Decoder

The boot ROM alias occupies the lowest 128 KiB of the processor address space, from $000000 through $01FFFF.

A 128 KiB region contains 2^17 byte addresses. Address lines A16..A1 may vary within the region. The processor also exposes A0, but drives it high in 16-bit mode; /UDS and /LDS select the byte lane. Address lines A23..A17 must all be low.

Existing REGION0 Decode

REGION0_n is already generated by the primary address decoder. When REGION0_n is active, address lines A23..A21 are known to be zero.

The low-128-KiB decoder therefore only needs to test address lines A20..A17.

Implementation

U_LOW128 is an SN74HCT138N. CPU address lines A18, A19, and A20 drive its select inputs. A17 and REGION0_n drive its active-low enables.

Address Condition

LOW128_n becomes active only when all of the following conditions are true:

REGION0_n = 0
A20 = 0
A19 = 0
A18 = 0
A17 = 0

Since REGION0_n already guarantees that A23..A21 are zero, this is equivalent to:

A23..A17 = 0000000

The resulting address range is exactly:

$000000-$01FFFF

Boundary Examples

Qualification Note

LOW128_n is a raw address-decode signal. It does not by itself select the firmware EEPROM and is not qualified by NORMAL_CYCLE_n.

The final ROM alias selection combines this signal with the boot overlay state and normal-cycle qualification.

U_LOW128 has a 100 nF capacitor and a 1 uF capacitor in parallel between VCC and GND, placed near the IC.

14. Boot Overlay State

One bit of motherboard state controls the boot ROM overlay. Hardware reset enables the overlay. A write to SYSREG0 / SYSCTRL disables it until the next hardware reset.

Overlay State Signals

The active-high signal OVERLAY_EN represents the current overlay state.

OVERLAY_EN = 1  -> boot ROM alias enabled
OVERLAY_EN = 0  -> boot ROM alias disabled

The complementary active-low signal is named OVERLAY_n.

OVERLAY_n = NOT OVERLAY_EN

Required Behavior

Implementation

U_OVERLAY, an SN74HCT74N, stores the overlay state. The first flip-flop uses its asynchronous preset and clear inputs, so no decode signal is used as a clock.

RESET_n and OVERLAY_WRITE_n must not be low together during normal operation. An asynchronous reset can arrive during an existing overlay-clear write. Verify that clear returns inactive while preset remains asserted and that the boot state is restored before CPU reset release. The boot-overlay reset checks include the two-stage SN74LS14 conditioner and the remaining loaded preset-edge check. RESET_RAW_n is confined to the supervisor, switch, capacitor, and first Schmitt input; RESET_n is the conditioned board-reset signal. A processor-generated /RESET pulse does not reach U_OVERLAY.

Write Behavior

The value written to SYSREG0 / SYSCTRL is ignored. Any valid write to the register disables the boot overlay.

write SYSREG0 / SYSCTRL -> OVERLAY_EN = 0

The register is intentionally one-way. Software cannot re-enable the boot overlay after it has been disabled. Only an external reset restores OVERLAY_EN to one.

Asynchronous State Change

Hardware reset drives 1/PRE low and sets OVERLAY_EN. A qualified write drives 1/CLR low and clears OVERLAY_EN. Releasing either asynchronous input leaves the stored state unchanged.

RESET_n = 0         -> OVERLAY_EN = 1
OVERLAY_WRITE_n = 0 -> OVERLAY_EN = 0

The clock-and-reset document defines the circuit that generates RESET_n. This decoder treats it as an active-low input.

Address Mirroring

Because the system-register decoder uses partial address decoding, SYSREG0 / SYSCTRL is electrically mirrored throughout I/O slot 4. A write to any mirror has the same hardware effect. Software uses $E80001 as the canonical overlay-control address.

The SN74HCT74N has a 100 nF capacitor and a 1 uF capacitor in parallel between VCC and GND, placed near the IC.

15. Boot ROM Alias Generation

The firmware EEPROM is temporarily mapped into the lowest 128 KiB of the processor address space while the boot overlay is enabled.

ROM_ALIAS_ADDR_n records the address and overlay state condition. ROM_ALIAS_n adds normal-cycle qualification.

Alias Address Condition

LOW128_n is active when the CPU address lies between $000000 and $01FFFF.

OVERLAY_n is active when the boot overlay is enabled. An OR gate combines the two active-low signals, so its output is low only when the address is inside the alias range and the overlay is enabled.

ROM_ALIAS_ADDR_n = LOW128_n OR OVERLAY_n

Bus Cycle Qualification

ROM_ALIAS_ADDR_n does not indicate an active CPU bus cycle. A second OR gate combines it with NORMAL_MISC_n to generate the qualified boot ROM alias request.

ROM_ALIAS_n = ROM_ALIAS_ADDR_n OR NORMAL_MISC_n

Reset Vector Example

Immediately after reset, OVERLAY_EN is high and OVERLAY_n is low.

A CPU access to $000004 activates LOW128_n. During a normal bus cycle the resulting signals are:

LOW128_n         = 0
OVERLAY_n        = 0
ROM_ALIAS_ADDR_n = 0
NORMAL_CYCLE_n   = 0
ROM_ALIAS_n      = 0

The firmware EEPROM owns the reset-vector access.

After Overlay Disable

After software writes to SYSREG0 / SYSCTRL, OVERLAY_EN becomes zero and OVERLAY_n becomes one.

An access to the same low address then produces:

LOW128_n         = 0
OVERLAY_n        = 1
ROM_ALIAS_ADDR_n = 1
NORMAL_CYCLE_n   = 0
ROM_ALIAS_n      = 1

The firmware EEPROM no longer responds through the low alias.

Signal Roles

16. Firmware ROM Cycle Selection

The firmware EEPROM has two address mappings. The permanent mapping occupies $FE0000-$FFFFFF. The temporary boot alias occupies $000000-$01FFFF while the boot overlay is enabled.

ROM_CYCLE_n combines both qualified selections into one active-low firmware request.

Input Signals

Logic Equation

An AND gate combines the two active-low inputs. Its output is low when either mapping selects the firmware EEPROM.

ROM_CYCLE_n = IO15_n AND ROM_ALIAS_n

Truth Table

Bus Cycle Qualification

ROM_CYCLE_n does not need another normal-cycle term. IO15_n is already generated by the qualified top I/O decoder, and ROM_ALIAS_n already includes NORMAL_MISC_n.

Permanent Mapping Example

During a normal access to $FE0100:

IO15_n      = 0
ROM_ALIAS_n = 1

ROM_CYCLE_n = 0 AND 1
            = 0

The firmware EEPROM is selected through its permanent mapping.

Boot Alias Example

Immediately after reset, a normal access to $000004 produces:

IO15_n      = 1
ROM_ALIAS_n = 0

ROM_CYCLE_n = 1 AND 0
            = 0

The firmware EEPROM is selected through the low boot alias.

After Overlay Disable

After the boot overlay has been disabled, an access to $000004 produces:

IO15_n      = 1
ROM_ALIAS_n = 1

ROM_CYCLE_n = 1 AND 1
            = 1

The firmware EEPROM no longer responds to the low address.

Implementation

Gate 3 in U_AND, an SN74HCT08N, generates ROM_CYCLE_n. Pins 9 and 10 are the inputs and pin 8 is the output.

ROM Bank and Byte-Lane Selection

Four AT28C256-15PU EEPROMs form a 128 KiB, 16-bit ROM. A16 selects one of two 64 KiB halves. Within each half, /UDS selects the upper-byte EEPROM and /LDS selects the lower-byte EEPROM.

A16_n        = NOT A16
READ_n       = NOT R/W

ROM_BANK0_n  = ROM_CYCLE_n OR A16
ROM_BANK1_n  = ROM_CYCLE_n OR A16_n

ROM0_UDS_n   = ROM_BANK0_n OR UDS_n
ROM0_LDS_n   = ROM_BANK0_n OR LDS_n
ROM1_UDS_n   = ROM_BANK1_n OR UDS_n
ROM1_LDS_n   = ROM_BANK1_n OR LDS_n

CPU A1..A15 connect to EEPROM A0..A14 on all four devices. On an upper-byte EEPROM, I/O0..I/O7 connect to CPU D8..D15. On a lower-byte EEPROM they connect to CPU D0..D7. Every EEPROM /OE input connects to READ_n, and every /WE input connects to +5 V.

A write to either firmware mapping cannot alter the EEPROM because /WE is held high. The firmware interface does not assert ROM_DTACK_n for a write, so the timeout ends the cycle with /BERR. Read timing and generation of ROM_DTACK_n belong in the firmware ROM document.

17. DRAM Bank 0 Overlay Suppression

DRAM bank 0 normally occupies $000000-$1FFFFF. During boot, however, the lowest 128 KiB of this region is temporarily occupied by the firmware ROM alias.

DRAM bank 0 must remain inactive while the boot ROM alias owns an address.

Base DRAM Bank 0 Request

Without overlay suppression, a normal access to REGION0 would generate:

RAM0_BASE_n = REGION0_n OR NORMAL_MEM_n

This signal cannot be the final DRAM bank 0 request because it would also become active during accesses to the boot ROM alias.

Alias Suppression Signal

ROM_ALIAS_ADDR_n is active low whenever the current address lies inside the low 128 KiB and the boot overlay is enabled.

An inverter produces an active-high version of this condition:

ALIAS_ACTIVE = NOT ROM_ALIAS_ADDR_n

When ALIAS_ACTIVE is high, DRAM bank 0 must remain inactive.

Final DRAM Bank 0 Request

RAM0_REQ_n = RAM0_BASE_n OR ALIAS_ACTIVE

Substituting the base request gives:

RAM0_REQ_n =
    REGION0_n
    OR NORMAL_MEM_n
    OR ALIAS_ACTIVE

Boot Vector Example

Immediately after reset, a CPU access to $000004 occurs inside the boot ROM alias.

REGION0_n        = 0
NORMAL_CYCLE_n   = 0
ROM_ALIAS_ADDR_n = 0
ALIAS_ACTIVE     = 1

RAM0_REQ_n       = 1

DRAM bank 0 remains inactive while the firmware EEPROM supplies the reset-vector data.

Access Above the Alias During Boot

The boot overlay affects only the lowest 128 KiB. An access to $100000 while the overlay is enabled produces:

REGION0_n        = 0
NORMAL_CYCLE_n   = 0
ROM_ALIAS_ADDR_n = 1
ALIAS_ACTIVE     = 0

RAM0_REQ_n       = 0

DRAM bank 0 remains usable above the boot ROM alias before the overlay is disabled.

Low Memory After Overlay Disable

After software disables the boot overlay, a CPU access to $000004 produces:

REGION0_n        = 0
NORMAL_CYCLE_n   = 0
ROM_ALIAS_ADDR_n = 1
ALIAS_ACTIVE     = 0

RAM0_REQ_n       = 0

DRAM bank 0 now owns the low address.

Implementation

ALIAS_ACTIVE requires one inversion of ROM_ALIAS_ADDR_n. The two-stage bank 0 request requires two 2-input OR gates.

One gate in U_INVERT, an SN74HCT04N, generates ALIAS_ACTIVE. Two gates in the SN74HCT32N OR-gate bank generate RAM0_BASE_n and RAM0_REQ_n.

Section 23 lists the package and pin assignments.

DRAM Controller Interface

RAM0_REQ_n is a request to the DRAM controller and is not connected directly to a DRAM /RAS or /CAS input.

DRAM row/column multiplexing, /RAS and /CAS timing, refresh, write control, and bus-cycle termination belong in the DRAM document.

18. Worked Decode Examples

These examples trace an address through each decoder that applies to it. A zero on a signal ending in _n means that the signal is active.

DRAM Bank 1 Read at $300000

For a normal read, AS_n is low and CPU_SPACE is low. Address bits A23..A21 = 001 select primary-decoder output /Y1.

AS_n             = 0
CPU_SPACE        = 0
NORMAL_CYCLE_n   = 0 OR 0 = 0
NORMAL_MEM_n     = 0

A23..A21         = 001
REGION1_n        = 0

RAM1_REQ_n       = REGION1_n OR NORMAL_MEM_n
                 = 0 OR 0
                 = 0

RAM1_REQ_n requests the transfer from the DRAM controller.

Debug Register Write at $E80003

This lower-byte write passes through the primary decoder, the low-half I/O decoder, and the system-register decoder.

AS_n             = 0
CPU_SPACE        = 0
NORMAL_CYCLE_n   = 0
NORMAL_MEM_n     = 0

A23..A21         = 111
REGION7_n        = 0
TOP_IO_n         = REGION7_n OR NORMAL_MEM_n
                 = 0 OR 0
                 = 0

A20              = 0       low-half I/O decoder enabled
A19..A17         = 100     /Y4 selected
IO4_n            = 0

LDS_n            = 0       system-register decoder enabled
A3..A1           = 001     /Y1 selected
SYSREG1_n        = 0

R/W              = 0
DEBUG_WRITE_n    = SYSREG1_n OR R/W
                 = 0 OR 0
                 = 0

The active DEBUG_WRITE_n signal identifies a write to SYSREG1 / DEBUG. The register captures data from D7..D0 when DEBUG_CLK rises during the write.

Upper-Byte Access at $E80002

The address still selects I/O slot 4, but an upper-byte access leaves LDS_n high. That disables U_SYSREG through its /G2B input.

IO4_n            = 0
UDS_n            = 0
LDS_n            = 1

SYSREG0_n..SYSREG7_n = 1
DEBUG_WRITE_n         = 1

No motherboard system register responds to this access.

Firmware Read at $FE0100

The permanent firmware mapping uses I/O slot 15. The boot-overlay state does not affect this mapping.

AS_n             = 0
CPU_SPACE        = 0
NORMAL_CYCLE_n   = 0
NORMAL_MEM_n     = 0

A23..A21         = 111
REGION7_n        = 0
TOP_IO_n         = 0

A20              = 1       high-half I/O decoder enabled
A19..A17         = 111     /Y7 selected
IO15_n           = 0

ROM_ALIAS_n      = 1
ROM_CYCLE_n      = IO15_n AND ROM_ALIAS_n
                 = 0 AND 1
                 = 0

ROM_CYCLE_n selects the firmware interface. The state of A16 and the byte strobes select one of the four EEPROMs.

CPU-Space Cycle at $E80003

The primary decoder always follows the address bus, so it still activates REGION7_n. The normal-cycle qualifier prevents the address from reaching either I/O slot decoder.

AS_n             = 0
FC2..FC0         = 111
CPU_SPACE        = 1
NORMAL_CYCLE_n   = AS_n OR CPU_SPACE
                 = 0 OR 1
                 = 1
NORMAL_MEM_n     = 1

REGION7_n        = 0
TOP_IO_n         = REGION7_n OR NORMAL_MEM_n
                 = 0 OR 1
                 = 1

IO0_n..IO15_n    = 1
SYSREG0_n..SYSREG7_n = 1

Normal memory, I/O, and system-register logic does not respond. The interrupt logic handles the CPU-space transaction separately.

19. Bus Cycle Termination

Address decoding determines which motherboard subsystem owns a CPU bus cycle. Bus-cycle termination tells the processor when that subsystem has completed the transfer.

The MC68EC000 uses the active-low /DTACK input to acknowledge completion of a normal bus transfer. The processor waits until the selected subsystem or its interface logic produces a valid termination response.

Selection and Completion

A device-select signal does not by itself indicate that the transfer is complete.

address decode -> target selected -> transfer
    -> completion response -> /DTACK -> cycle complete

Each subsystem can assert /DTACK when its transfer completes, so slower subsystems add wait states without imposing the same delay on faster devices.

Subsystem Termination Responsibility

Internal Completion Signals

Each subsystem generates one internal active-low completion signal. An adapter may generate the signal when the device does not provide a 68k-compatible acknowledgement output.

DRAM_DTACK_n
ROM_DTACK_n
SYSREG_DTACK_n
MFP_DTACK_n
FDC_DTACK_n
OPL3_DTACK_n
VGA_DTACK_n
MIDI_DTACK_n
RTC_DTACK_n
EXP_DTACK_n

An unselected subsystem must keep its completion signal inactive. A subsystem must never terminate a bus cycle that it does not own. Once asserted, a completion signal remains low until AS_n returns high.

Final /DTACK Combination

Two SN74F21N packages combine the ten completion signals through four-input AND gates. No device outputs are connected together. The SN74F21N is a period-correct 5 V TTL dual four-input AND in a 14-pin PDIP; its TI data sheet dates from 1987 and was revised in 1993. FAST rather than HCT is required here so that the acknowledgement-release path fits inside the MC68EC000FN10 requirement of 110 ns from AS_n or the data strobes negating to /DTACK negating.

Because the individual completion signals are active low, the logical behavior is equivalent to an AND of the inactive-high responses:

DTACK_GROUP0_n =
    DRAM_DTACK_n AND ROM_DTACK_n
    AND SYSREG_DTACK_n AND MFP_DTACK_n

DTACK_GROUP1_n =
    FDC_DTACK_n AND OPL3_DTACK_n
    AND VGA_DTACK_n AND MIDI_DTACK_n

DTACK_GROUP2_n = RTC_DTACK_n AND EXP_DTACK_n AND 1 AND 1

DTACK_RAW_n =
    DTACK_GROUP0_n AND DTACK_GROUP1_n
    AND DTACK_GROUP2_n AND 1

DTACK_n = DTACK_RAW_n OR TIMEOUT_ACTIVE

The MC68901 MFP_DTACK_n input in group 0 terminates both ordinary MFP register cycles and level-6 interrupt-acknowledge cycles. The completion tree remains active during CPU space, while the normal bus timeout does not run there.

Pin 7 of each package connects to ground and pin 14 connects to +5 V. The three unused gate inputs shown as logic one connect to +5 V: pins 4 and 5 on U_DTACK_B gate 1 and pin 13 on gate 2. EXP_DTACK_n has a 10 kohm pull-up at the motherboard and the expansion card may only pull it low. The timeout circuit masks DTACK_RAW_n after a bus error and drives the CPU /DTACK pin with DTACK_n.

The final DTACK_n = DTACK_RAW_n OR TIMEOUT_ACTIVE mask is one gate of U_OR_DTACK, an SN74F32N. It is a dedicated FAST-family OR package rather than a gate of the SN74HCT32N bank, so the release edge is not slowed by the slower HCT part. SN74F32N is period-correct, 5 V, and available in PDIP.

Acknowledgement Release Path

The MC68EC000FN10 requires /DTACK to negate no later than 110 ns after AS_n and the data strobes negate. When a subsystem releases its completion signal, that rising edge propagates to the CPU /DTACK pin through the FAST tree only:

subsystem DTACK_n rises
    -> SN74F21 level 1 (group AND)   <= 5.3 ns   tPLH
    -> SN74F21 level 2 (final AND)   <= 5.3 ns   tPLH
    -> SN74F32 timeout OR mask       <= 6.6 ns   tPLH
    -> CPU DTACK_n rises

global release-tree logic delay     <= 17.2 ns

Each stage uses the low-to-high datasheet maximum because release is a rising edge at every node in the path: tPLH(SN74F21) = 5.3 ns and tPLH(SN74F32) = 6.6 ns. Assertion is the falling-edge direction and uses tPHL(SN74F21) = 5.5 ns and tPHL(SN74F32) = 6.3 ns; assertion delay is allowed to add a CPU wait state, so it is not on the 110 ns critical path.

The 17.2 ns figure is the shared motherboard logic only. It does not by itself prove the full CPU /DTACK negation timing. Each subsystem still adds its own local release-qualification logic, and PCB trace, connector, and loading delay must be added on top. Those contributions are accounted for on the individual subsystem pages and in the final board timing review.

Subsystem Timing

Each subsystem document defines the earliest safe assertion of its completion response. This gives each device the shortest safe bus cycle instead of imposing one wait-state count on the whole board.

For example, the DRAM controller asserts its response only after the required row and column sequence has completed, while the firmware ROM interface must allow sufficient time for EEPROM read data to become valid.

CPU Space Cycles

The normal motherboard termination paths described in this section apply to ordinary memory and I/O cycles. The interrupt interface handles CPU-space transactions such as interrupt acknowledge.

Unanswered Cycles

If no selected subsystem produces a completion response, the processor is not left waiting indefinitely. The bus-timeout circuit terminates the unanswered cycle using /BERR.

Section 20 documents bus error and timeout behavior.

20. Bus Error and Timeout

A normal CPU bus cycle may target an address for which no installed motherboard or expansion device can respond. If no subsystem asserts /DTACK, a bus timeout must terminate the transaction with /BERR.

Successful and Failed Termination

/DTACK and /BERR represent two different outcomes of a bus transaction.

Timeout Behavior

The timeout mechanism begins monitoring when a normal bus cycle becomes active.

normal bus cycle begins -> start timeout monitoring

If /DTACK is asserted before the timeout expires, the transfer completes normally. The CPU then releases AS_n, which resets the counter.

/DTACK before timeout -> normal completion
    -> AS_n released -> timeout counter reset

If the bus cycle remains active and no /DTACK response is received before the timeout expires, the timeout logic generates a bus error.

no /DTACK before timeout -> TIMEOUT_BERR_n = 0
    -> /BERR asserted

Timeout Bus Error Source

The internal active-low signal TIMEOUT_BERR_n represents a bus error caused specifically by an unanswered normal bus cycle.

TIMEOUT_BERR_n = 0
    -> current normal bus cycle exceeded the allowed response time

TIMEOUT_BERR_n is combined with INT_BERR_n from the interrupt logic in U_AND gate 4; the result BERR_n drives the processor's physical /BERR input. The timeout does not assert /HALT.

Normal Cycle Qualification

Timeout monitoring starts only when NORMAL_CYCLE_n goes low.

Raw address-decoder outputs such as REGION2_n do not start timeout monitoring because they do not by themselves indicate that a CPU bus cycle is active.

Unmapped Address Example

Consider a normal CPU access to $500000 with no expansion hardware installed in the corresponding address region.

normal bus cycle begins
REGION2_n = 0

no installed target responds
no subsystem generates /DTACK

timeout expires

TIMEOUT_BERR_n = 0
/BERR asserted

The CPU receives a bus error instead of waiting for nonexistent hardware.

Timeout Duration

The timeout uses 512 falling edges of the 10 MHz clock. Depending on the phase of AS_n, TIMEOUT_ACTIVE rises about 51.1 to 51.2 microseconds after a normal cycle begins, plus counter propagation delay.

Each valid device adapter must assert its completion response before this boundary. Software-visible device busy times do not extend a bus cycle; software polls the device status instead.

Implementation

U_TIMEOUT, a CD74HCT4040E counter, counts falling edges of the 10 MHz clock while a normal cycle is active. Its master reset connects to NORMAL_MISC_n.

TIMEOUT_ACTIVE = U_TIMEOUT Q10
TIMEOUT_BERR_n = NOT TIMEOUT_ACTIVE
BERR_n         = TIMEOUT_BERR_n AND INT_BERR_n
DTACK_n        = DTACK_RAW_n OR TIMEOUT_ACTIVE

INT_BERR_n is the spurious-interrupt-acknowledge abort from the interrupt logic. It is inactive during normal cycles. U_AND gate 4 combines the two active-low bus-error sources; either one asserts the processor /BERR input.

Once TIMEOUT_ACTIVE rises, the U_OR_DTACK SN74F32N gate forces DTACK_n high even if a late device response arrives. The inverter asserts BERR_n low. When the CPU releases AS_n, NORMAL_MISC_n resets the counter, releases BERR_n, and removes the acknowledgement mask.

CPU Space Cycles

The timeout mechanism described here applies to normal memory and I/O cycles. The interrupt interface handles CPU-space transactions, including interrupt acknowledge.

21. Interrupt Acknowledge Separation

Interrupt acknowledge is a CPU-space transaction, so it is excluded from normal memory and I/O requests. The MC68000 function-code table assigns FC2..FC0 = 111 to CPU space.

CPU_SPACE = FC2 AND FC1 AND FC0

Section 7 defines the normal bus qualifier as:

NORMAL_CYCLE_n = AS_n OR CPU_SPACE

During an active CPU-space transaction, CPU_SPACE is high. This forces NORMAL_CYCLE_n inactive even while /AS is asserted.

CPU Space Example

AS_n           = 0
FC2..FC0        = 111
CPU_SPACE       = 1

NORMAL_CYCLE_n  = 0 OR 1
                = 1

Qualified memory and I/O requests remain inactive during the CPU-space transaction.

Effect on Qualified Device Requests

Because normal device requests are qualified using NORMAL_CYCLE_n, ordinary motherboard devices do not respond during CPU-space cycles.

This includes DRAM, firmware ROM, CL-GD5428 VGA memory, the I/O slot decoder, and motherboard system registers.

CPU-space cycle -> NORMAL_CYCLE_n inactive
    -> normal RAM, ROM, and I/O requests remain inactive

Interrupt Acknowledge Handling

Interrupt-acknowledge transactions are handled by separate interrupt logic rather than by the normal address decoder.

The interrupt document defines the /IPL2..IPL0 priority inputs, the acknowledge decode, and vector generation. Interrupt logic must never assert /DTACK and /AVEC at the same time.

Three signals from the interrupt logic reach the processor through this document's circuits:

The interrupt logic also adds one input load to CPU_SPACE, AS_n, and CPU address lines A1..A3 and A16..A19. The bus timeout does not run during a CPU-space cycle, so the interrupt logic provides the only acknowledge-cycle backstop through INT_BERR_n.

22. Device Interface Boundaries

The motherboard decoder supplies one request or slot select to each subsystem. Each subsystem document defines its local register map, read and write strobes, data-bus wiring, and the earliest safe completion response.

The fixed-device slots use their low address bits for local register selection and otherwise mirror through the slot. Reserved selects do not reach the connectors. Empty expansion ranges produce no EXP_DTACK_n response, so the motherboard timeout reports a bus error.

23. Glue-Logic Package Assignments

The assignments below cover the motherboard bus and decoder. They do not include the DRAM controller, device adapters, expansion buffers, interrupt logic, or hexadecimal display decoder.

Decoder and Storage Packages

SN74HCT32N Gate Map

On each OR-gate package, gate 1 uses input pins 1 and 2 with output pin 3; gate 2 uses pins 4 and 5 with output pin 6; gate 3 uses pins 9 and 10 with output pin 8; and gate 4 uses pins 12 and 13 with output pin 11. Pin 7 is ground and pin 14 is +5 V.

Pins 9, 10, 12, and 13 of U_OR6 connect to ground and its unused output pins 8 and 11 remain open. The final DTACK_n timeout mask has its own FAST package, U_OR_DTACK (SN74F32N), described in the SN74F32N gate map below.

SN74F21N Acknowledgement-Tree Gate Map

On each SN74F21N, gate 1 uses input pins 1, 2, 4, and 5 with output pin 6; gate 2 uses input pins 9, 10, 12, and 13 with output pin 8. Pin 3 and pin 11 are not connected internally. Pin 7 is ground and pin 14 is +5 V. The pin-by-pin signal assignment is in the acknowledgement-tree connections table above. Unused inputs shown as logic one connect to +5 V.

SN74F32N Gate Map

U_OR_DTACK uses gate 1 only: input pins 1 and 2 carry DTACK_RAW_n and TIMEOUT_ACTIVE, and output pin 3 is DTACK_n to the processor /DTACK pin. Gates 2 through 4 are unused; their input pins 4, 5, 9, 10, 12, and 13 connect to ground and their output pins 6, 8, and 11 remain open. Pin 7 is ground and pin 14 is +5 V.

SN74HCT04N Gate Map

Gate 5 input pin 11 connects to DEBUG_WRITE_n. Gate 6 is unused: tie pin 13 to ground and leave pin 12 open. The DRAM page owns both divider-reset functions because normal refresh starts only after initialization. Pin 7 is ground and pin 14 is +5 V.

SN74HCT574N Debug Register

Power and Sockets

Every logic IC is socketed. Each package has a 100 nF ceramic capacitor and a 1 uF capacitor in parallel between its supply pins, placed beside the socket. Every unused logic input is tied to ground or +5 V as listed above; unused outputs remain open.

24. Decoder Timing Verification

This section records the maximum propagation delay through the current address-decoder design. It covers the shared glue logic. Each device page adds its target access time, wait-state generation, and local /DTACK timing.

Conditions and Method

The motherboard uses a nominal +5 V supply. The SN74HCT calculations use the TI switching limits at VCC = 4.5 V, CL = 50 pF, and TA = -40 C to +85 C. The 4.5 V limits are the conservative datasheet values for the permitted SN74HCT supply range. The SN74F21N and SN74F32N in the acknowledgement path are FAST-family TTL parts; their delays below are the commercial SN74F21 (SDFS006A) and SN74F32 (SDFS044B) MIN-to-MAX-column maxima at CL = 50 pF, RL = 500 ohm, and VCC = 4.5 V to 5.5 V. That column is characterized only over TA = 0 C to +70 C: the N-package SN74F parts do not carry the -40 C to +85 C rating used for the SN74HCT glue; see the FAST-family temperature note in section 25. Each complete-path total is the sum of the applicable maximum delays; it does not include trace delay, output loading above 50 pF, or input skew.

The SN74HCT tables specify tpd, defined by the measurement diagram as the greater of tPLH and tPHL. Therefore one maximum value safely covers assertion and release for each HCT stage. The SN74F21 and SN74F32 rows list tPLH and tPHL separately; the acknowledgement-release (negation) path is a rising edge at every node, so it uses the tPLH figures, and the assertion path uses tPHL.

Single-Stage Delays

The full TIMEOUT_ACTIVE to BERR_n path is now 55 ns through the inverter and the combining gate. The bus timeout is a 51.2 microsecond event, so this added stage does not affect when the processor sees /BERR.

The CPU_SPACE delay is 60 ns from FC2 or FC1 because those inputs pass through both gates. The delay from FC0 is 30 ns because it passes through only the final gate.

Multi-Stage Decode Paths

Each broad address range above reports its longest input route. For example, an A20..A18 change reaches ROM_ALIAS_n through the 45 ns select path of U_LOW128, while an A23..A21 change first passes through U_PRIMARY and then uses the 42 ns enable path of U_LOW128.

Timing Boundary

The totals above end at the motherboard request outputs or begin at a subsystem completion input. Each subsystem document adds its local decode, device access time, and completion generation. Every adapter must keep its full response below the 51.1 microsecond minimum timeout boundary.

For the acknowledgement-release direction the constraint is the MC68EC000FN10 limit of 110 ns from AS_n or the data strobes negating to /DTACK negating. The shared motherboard contribution is the 17.2 ns FAST release tree (SN74F21 + SN74F21 + SN74F32, all low-to-high). This is logic delay only and does not on its own prove the CPU-pin timing: each subsystem adds its own local release-qualification logic ahead of its completion output, and PCB trace, connector, and receiver loading delay must be added. Those are resolved on the subsystem pages and in the final board timing review.

Measure each complete release path on the assembled board at the CPU pin. The pass limit is 110 ns from AS_n or both data strobes negating to DTACK_n high. The DRAM path has 28.5 ns of verified logic delay and an 81.5 ns allowance for receiver, interconnect, and loading; see DRAM release timing.

The firmware chip select takes at most 237 ns from the address path or 252 ns from the function-code qualification path. The AT28C256 then needs as much as 150 ns to produce valid data. The firmware interface therefore supplies the required wait states instead of acknowledging the cycle directly from ROM_CYCLE_n.

These calculations use the SN74HCT -40 C to +85 C values and a 50 pF test load, except the SN74F21 and SN74F32 release-tree stages, which use the 0 C to +70 C SN74F N-package limits (see the FAST-family temperature note in section 25). Section 25 also defines how socket, trace, and receiver capacitance are checked when each subsystem schematic is completed.

25. Electrical Compatibility and Fanout

This section verifies logic levels and static-current fanout within the address-decode network. It does not include memory, peripheral, expansion, connector, or PCB trace loading.

Verification Rules

HIGH noise margin = VOH(min) - VIH(min)
LOW noise margin  = VIL(max) - VOL(max)

A connection is statically compatible when both margins are zero or greater. Fanout is checked by comparing the sum of receiver input currents with the output current at which the driver guarantees its stated VOH or VOL.

Datasheet Limits

The HCT values above are common to the project datasheets for the SN74HCT04, SN74HCT08, SN74HCT32, and SN74HCT138 at the stated test conditions. The SN74F input and output values are common to the SN74F10, SN74F21, and SN74F32 data sheets; the N-package parts state no input capacitance and are characterized only over TA = 0 C to +70 C.

CPU-to-HCT Compatibility

The high-level calculation uses the minimum CPU supply of 4.75 V: 4.75 V - 0.75 V = 4.00 V. The low-level voltage is the same for the CPU output groups used by the decoder, although their guaranteed sink currents differ.

HCT-to-HCT Compatibility

FAST-Family Compatibility

The acknowledgement AND tree (U_DTACK_A, U_DTACK_B, SN74F21N) and the timeout OR mask (U_OR_DTACK, SN74F32N) are FAST TTL. The DRAM completion driver U_DRAM_DTACK_GATE (SN74F10N, documented on the DRAM page) shares the same DC limits. The voltage checks below use the rated-current worst-case values from the Datasheet Limits table.

The high margin uses the 2.50 V FAST VOH(min) at VCC = 4.5 V; at a nominal 5 V rail the guaranteed VOH is 2.7 V or higher, so 0.50 V is a floor. Every FAST driver in the path also meets the CPU's VIL(max) with 0.30 V of low-side margin, the same figure the CPU-to-HCT check carries.

The binding FAST current is the 0.6 mA LOW input current (IIL) that each SN74F input can pull from its driver. No net in the acknowledgement tree presents more than one FAST load to an SN74F21 or SN74F32 output, and each of those outputs sinks 20 mA, so the sink ratio never falls below about 33. AS_n, UDS_n, and LDS_n gain FAST loads at U_DRAM_DTACK_GATE; that budget is on the DRAM page because those strobes are decoded there.

FAST-Family Temperature Range

The N-package SN74F10, SN74F21, and SN74F32 are characterized only over TA = 0 C to +70 C. This is the motherboard's specified operating range because the design requires plastic through-hole FAST parts. The HCT devices have wider published ranges, but that does not widen the assembled motherboard rating.

Static-Current Fanout

Each HCT input contributes at most 1 uA of leakage magnitude. The current checks below cover the documented decode-network loads only. Each named stage is one of the package assignments above.

The smallest calculated CPU source-current ratio is on R/W: 400 uA / 10 uA, or 40. The smallest HCT current ratio is on a four-load normal-cycle copy: 6000 uA / 4 uA, or 1500. Static-current fanout is therefore not the limiting factor for the defined network.

Capacitive Loading

The capacitance totals use the 10 pF maximum for each HCT input. They exclude package sockets, traces, vias, connectors, and measurement probes. The four-load normal-cycle copies have the least remaining margin. Keep each completed HCT net at or below 50 pF, or add another HCT buffer and recalculate its timing.

Each of A16..A1 also gains two HCT244 inputs from the expansion interface, for at most 20 pF added receiver capacitance and 2 uA added leakage per line. Add these to the line's device-specific consumers when checking the complete motherboard.

The SN74F10, SN74F21, and SN74F32 data sheets state no input capacitance. The FAST acknowledgement nets each carry one FAST load and a short motherboard trace, so they stay well inside the 50 pF, 500 ohm switching-test load; the exact receiver plus trace figure is confirmed in the final board load audit alongside the HCT nets.

Subsystem Integration Rules

26. Internal Signal Reference

This reference lists named signals generated or consumed by the motherboard bus-and-decode logic. Names ending in _n are active low. Other names are active high unless their description says otherwise.

CPU pins such as A23..A0, FC2..FC0, AS_n, and R/W are external inputs to this logic and are not listed as internal signals. Package pin names such as /Y0 are not separate reference entries. The package names match the assignments in this document.

Cycle and Address Decode

Overlay, ROM, and DRAM Control

Bus Completion and Error Signals

Subsystem completion names describe logical active-low responses. They are not necessarily pins on the named peripheral.

27. Sources

• Motorola, M68000 User's Manual, sections 3.1 through 3.9 (bus signals and function codes), 5.1.4 (CPU space), 10.13 (DC characteristics and capacitance), and 10.14 (MC68EC000 10 MHz AC characteristics); and the manual addendum.
• Texas Instruments, SN74HCT138, SN74HCT08, SN74HCT32, SN74HCT04, SN74HCT244, SN74HCT74, and SN74HCT574. Decoder, glue, overlay, buffer, and debug-register limits.
• Texas Instruments, SN74F21 (SDFS006A), SN74F32 (SDFS044B), and SN74F10 (SDFS039A). Acknowledgement-tree and timeout-mask timing and DC limits.
• Texas Instruments, CD74HCT4040. Bus-timeout counter pinout and ripple delay.
• Microchip, AT28C256. Firmware EEPROM access time used in the decode-path budget.
• The project Memory Map fixes every address range this decoder implements. The DRAM, Firmware ROM, Interrupts, Clock and Reset, and per-device pages own the timing behind each request and completion signal.