CL-GD5428 VGA

1. Purpose and Scope

The CL-GD5428 is a VGA controller with a 32-bit BitBLT engine, a programmable dual-frequency synthesizer, and an integrated 24-bit palette DAC. It drives 2 MiB of its own display memory and produces analog RGB with separate horizontal and vertical sync. This board operates it in ISA bus mode, which uses asynchronous MEMR*, MEMW*, IOR*, and IOW* strobes with an IOCHRDY wait output. The local-bus modes require a synchronous 386 or 486 protocol with ADS# and RDYRTN#, which the MC68EC000 does not produce.

The Memory Map owns the host-memory window and I/O slot 3. Bus and Address Decode owns VGA_MEM_n, IO3_n, the completion tree, and timeout behavior. The Clock and Reset design owns PERIPH_RESET_n. The MC68901 MFP owns GPIP2 and the interrupt vector. This page owns the address translation, bus adapter, wait handling, display memory, configuration EEPROM, dedicated clock, reset polarity, and analog output.

Mode setting, palette loading, BitBLT programming, and the hardware cursor belong to firmware. This page defines what the hardware makes reachable and the rules firmware must obey to reach it.

Signal names ending in _n, and names written with a leading slash, are active low. Cirrus Logic writes its own active-low names with a trailing asterisk, and this page keeps that spelling for controller pins. Logic uses +5 V. Every IC family selected here existed before 1994. The CL-GD5428 has no DIP version and mounts directly to the motherboard, as do the four display-memory DRAMs.

2. Architecture

MC68EC000                              CL-GD5428 (ISA bus mode)

D15..D8 <--------------------------> SD7..SD0
D7..D0  <--------------------------> SD15..SD8
A23..A17 -------------------------> LA23..LA17
A16..A1  -------------------------> SA16..SA1
UDS_n ----------------------------> SA0
LDS_n ----------------------------> SBHE*
VGA_MEM_n, IO3_n, R/W ------------> adapter
AS_n, UDS_n, LDS_n ---------------> adapter
VGA_CLK_14 --> U_VGA_SEQ ---------> BALE, MEMR*, MEMW*, IOR*, IOW*
IOCHRDY --> U_VGA_SYNC -----------> wait hold
adapter completion ---------------> VGA_DTACK_n
PERIPH_RESET_n --> inverter ------> RESET
                          +5 V ---> REFRESH*, TWR*, EDCLK*
                           GND ---> AEN

Y_VGA_CLK 14.31818 MHz --> R_VGA_CLK --> OSC
                        --> U_VGA_INV_B --> VGA_CLK_14

CL-GD5428                              four 256K x 16 DRAMs

RAS*, OE* as RAS1* ---------------> bank 0 and bank 1 RAS*
CAS* as WE* ----------------------> all four WE*
WE3..WE0* as CAS3..CAS0* ---------> upper and lower CAS* of each device
MA8..MA0 -------------------------> ADDR8..ADDR0
MD31..MD16 -----------------------> bank data, planes 2 and 3
MD15..MD0  -----------------------> bank data, planes 0 and 1
MD28, MD25 --> 6.8 kohm pull-downs --> configuration straps

CL-GD5428                              output and storage

RED, GREEN, BLUE --> 150 ohm --> pi filter --> DE-15 pins 1, 2, 3
HSYNC ----------------------------------------> DE-15 pin 13
VSYNC ----------------------------------------> DE-15 pin 14
                                             +-> MC68901 GPIP2
IREF <-- Q_VGA_IREF collector, 6.6 mA sink
EECS, ESYNC*, EVIDEO*, EEDI ------------------> U_VGA_CFG NM93C46N

The adapter runs from the same 14.31818 MHz reference the controller uses for its internal synthesizer. One shift register produces the address-latch pulse, the command strobe, and the completion instant. Display-memory cycles additionally wait for IOCHRDY, which the controller drives low while a display-memory transfer is still in progress.

3. Bus Interface

Byte Lanes

The CL-GD5428 orders bytes little-endian and the MC68EC000 orders them big-endian, so the two 8-bit halves of the data bus cross. CPU D15..D8 carries the even byte, which the controller expects on SD7..SD0. CPU D7..D0 carries the odd byte, which the controller expects on SD15..SD8.

The byte enables cross with the data. The controller decodes width and alignment from SBHE* and SA0, and the two MC68EC000 data strobes supply both directly with no gates.

CL-GD5428 SA0   = UDS_n
CL-GD5428 SBHE* = LDS_n

A byte at MC68EC000 address N therefore reaches controller byte address N. No address arithmetic and no software byte swapping are needed at either aperture.

Cycle Qualification

VGA_MEM_n and IO3_n already include NORMAL_CYCLE_n, so neither asserts during a CPU-space cycle. The adapter adds the requirement that at least one byte strobe is active.

VGA_DS_n  = UDS_n AND LDS_n
VGA_SEL_n = VGA_MEM_n AND IO3_n
VGA_CYCLE = NOT (VGA_SEL_n OR VGA_DS_n)

On a write the MC68EC000 asserts its data strobes one clock after AS_n, so VGA_CYCLE starts one clock later than on a read. The adapter measures every interval from VGA_CYCLE, so the write data is already valid when the command strobe asserts.

4. Address Apertures

Because the address path passes through unchanged, the controller sees the processor's own address. Firmware places the controller's linear display-memory aperture at the same place the memory map already reserves for it, and the two agree without translation hardware.

Host-Memory Window

SR7[7:4] selects which 1 MiB segment of the 16 MiB address space the controller claims, comparing the field against address bits 23 through 20. Setting GRB[5] extends the claim to a 2 MiB range aligned on a 2 MiB boundary, and SR7[4] becomes a don't care. Programming SR7[7:4] to 1000 with GRB[5] = 1 makes the controller claim $800000-$9FFFFF, which is exactly REGION4 and exactly the 2 MiB of installed display memory.

The window is fully populated. There is no aliased region and no unmapped region inside it. The controller's own address decode answers every access the motherboard forwards.

SR7 resets to $00, which configures a standard VGA responding at $0A0000-$0BFFFF. That range is DRAM bank 0 on this board and is never presented to the controller, so between reset and the firmware write that sets SR7[7:4], the controller claims nothing in the host window. Reads there return the floating bus and writes are discarded. The firmware contract in section 12 makes enabling linear addressing a precondition for using the window.

Register Window

The controller decodes SA15..SA0 for I/O accesses and ignores LA23..LA17 and SA16. Slot 3 begins at $E60000, so the low 16 address bits of any access in $E60000-$E6FFFF are the VGA I/O port number, and the straight-through address path delivers them with no multiplexer.

VGA I/O port P appears at MC68EC000 byte address $E60000 + P

Every port sits in the first 64 KiB of the slot. A16 is not decoded, so the port map repeats once in the upper half of the slot, and firmware uses the copy listed above. Accesses to slot 3 addresses that no port claims receive completion from the adapter and transfer nothing useful, which matches how an unclaimed ISA I/O address behaves.

Aperture Summary

VGA_MEM_SEL = NOT VGA_MEM_n
VGA_IO_SEL  = NOT IO3_n

5. Bus Adapter and Wait Handling

U_VGA_SEQ is a CD74HCT164E clocked by VGA_CLK_14. Its active-low clear connects to VGA_AS_ACTIVE, so all stages hold at zero whenever AS_n is high. Both serial inputs connect to VGA_CYCLE, so shifting begins only after the address, the select, and a byte strobe are all present.

Address Latch Enable

The controller latches LA23..LA17 on the falling BALE edge and needs 20 ns of setup, 20 ns of hold, and a 20 ns pulse. Driving BALE from the first shift stage gives one full clock period, 69.8 ns, for each of the three.

VGA_BALE = NOT QA

Command Strobes

The strobes assert one clock after BALE falls, which keeps the ISA address phase and command phase in the order the controller expects.

VGA_RW_n = NOT R/W
VGA_RD   = QB AND R/W
VGA_WR   = QB AND VGA_RW_n

VGA_MEMR_n = NOT (VGA_RD AND VGA_MEM_SEL)
VGA_MEMW_n = NOT (VGA_WR AND VGA_MEM_SEL)
VGA_IOR_n  = NOT (VGA_RD AND VGA_IO_SEL)
VGA_IOW_n  = NOT (VGA_WR AND VGA_IO_SEL)

VGA_MEM_SEL and VGA_IO_SEL both fall when AS_n rises, because their sources include NORMAL_CYCLE_n. Every strobe therefore negates at the end of the processor cycle without a separate release term. The MC68EC000 holds write data past AS_n negation, which covers the controller's 10 ns data hold from IOW* or MEMW* going inactive.

Wait Handling

IOCHRDY is a three-state output. On a display-memory read the controller drives it low within 28 ns of MEMR* and raises it when the data is ready. On a display-memory write it drives it high immediately if the write buffer has space, and low until space appears if it does not. It is never driven during I/O cycles, and it floats between cycles. R_VGA_RDY, 1 kohm to +5 V, defines the floating state and keeps the rising edge inside one clock period at the expected trace capacitance.

U_VGA_SYNC is an SN74HCT74N used as a two-stage synchronizer on VGA_CLK_14. Both active-low clears connect to VGA_CYCLE, so the pair starts from zero at each new cycle. The first stage samples IOCHRDY, the second stage samples the first, and the second stage output is VGA_READY.

U_VGA_SYNC stage 1 D = IOCHRDY
U_VGA_SYNC stage 2 D = stage 1 Q
VGA_READY = U_VGA_SYNC stage 2 Q

The first sample that can see a controller-driven level happens at QC, one clock period after the strobe asserted at QB. The controller guarantees the level within 28 ns, leaving 41.8 ns of setup, far beyond the SN74HCT74N requirement. The synchronizer therefore never samples a transition, and no completion decision rests on a metastable resolution.

Waiting two stages costs two clock periods after IOCHRDY rises. A display-memory read whose data is ready before QC completes at QE with no added wait.

Completion

VGA_AS_ACTIVE = NOT AS_n

VGA_QE_MEM    = QE AND VGA_MEM_SEL
VGA_MEM_DONE  = VGA_QE_MEM AND VGA_READY
VGA_IO_DONE   = QE AND VGA_IO_SEL

VGA_ACK_READY = VGA_MEM_DONE OR VGA_IO_DONE
VGA_DTACK_n   = NOT (VGA_AS_ACTIVE AND VGA_ACK_READY)

Both paths complete at QE so that they share one timing reference and neither races the synchronizer.

Gating completion with VGA_AS_ACTIVE holds VGA_DTACK_n low if the processor releases its data strobes before AS_n, and releases it from AS_n through two gates.

A display-memory read can wait as long as the controller needs, and the wait length depends on the video mode and on contention with screen refresh. The motherboard timeout of at least 51.1 us is the backstop.

Static Host Inputs

6. Configuration Straps

The controller latches configuration register CF1 from MD30..MD16 on the falling edge of RESET. Internal 250 kohm pull-ups make every bit read as one, and a 6.8 kohm external pull-down makes a bit read as zero. The memory data pins are forced high impedance while RESET is active so the pull-downs win, and the display-memory DRAMs cannot drive them because the controller holds its own RAS* and CAS* outputs inactive.

This design needs two zeros, so it installs two resistors.

CF[1] stays high, disabling 0WS*. That pin exists to shorten ISA host cycles and this adapter derives its own timing, so leaving it disabled removes one output that would otherwise need a pull-up.

7. Display Memory

The controller drives a 32-bit display-memory bus and supports 256K x 4, 512K x 8, and 256K x 16 organizations up to 2 MiB. It presents nine address lines in the symmetric configurations, so a 1M x 4 device such as the TMS44400 used for main memory cannot be wired as display memory.

Four 256K x 16 dual-CAS* devices give the full 2 MiB in four packages and fill the host window exactly. Each device must have separate lower and upper column-address strobes, one write enable, one output enable, nine symmetric address inputs, and a 70 ns row access time. The HM514260CJ7 is the specified device; the TRM characterizes it in its own 70 ns DRAM table.

With CF[12] low the controller renames three pin groups. WE3..WE0* become CAS3..CAS0*, CAS* becomes WE*, and OE* becomes RAS1*. Each DRAM output enable ties to ground, because the controller gates reads with the column strobes. MA9, pin 143, has no function in this configuration and is left open.

The controller refreshes display memory from its internal counter. No motherboard refresh signal reaches it, and REFRESH* stays high.

MCLK Selection

Strapping 41.16477 MHz gives a 24.29 ns memory clock. The TRM's standard-RAS* formulas resolve to the times below, all of which exceed what a 70 ns device requires.

The remaining column and write parameters fall between the 41.2 MHz and 43.0 MHz columns of TRM table B19-1, and every one of them clears the 70 ns requirements in table B19-4. The next faster strap, 44.74431 MHz, brings tRC down to 134.1 ns against a 130 ns requirement and is not used.

Firmware may reprogram MCLK through SR1F[5:0]. Doing so overrides the strap and moves every number in the table above, so firmware that changes MCLK owns the resulting DRAM timing.

8. Clock and Reset

Dedicated Reference Oscillator

Y_VGA_CLK is a packaged 14.31818 MHz clock oscillator. Any oscillator meeting the specification below is acceptable. The Epson SG-615 series is the reference part and the source of the output levels checked below; the ECS ECS-100AX-143 is an equivalent alternative if the Epson part cannot be sourced. Its output reaches CL-GD5428 OSC, pin 159, through R_VGA_CLK, a 33 ohm source-series resistor, and reaches U_VGA_INV_B for the adapter clock. Oscillator enable is tied high. XTAL, pin 158, is left open because no crystal is fitted.

The controller requires 14.31818 MHz within 0.01 percent at a duty cycle of 50 percent plus or minus 10 percent. The tolerance above, 100 parts per million, is 0.01 percent, and the symmetry limit above is 40 to 60 percent. Both parameters meet the requirement with no margin, so both appear on the assembled-board measurement list. An oscillator with a tighter tolerance or symmetry than the minimum specified is preferred where one is available.

The OPL3 uses a separate oscillator at the same frequency and to the same specification. Sharing one oscillator would put the video PLL reference and the audio master clock on the same net, so each subsystem keeps its own.

Y_VGA_CLK
    |
    +-- R_VGA_CLK --> CL-GD5428 OSC, pin 159
    |
    +-- U_VGA_INV_B stage 1 --> stage 2 --> VGA_CLK_14
                                              |
                                              +-- U_VGA_SEQ CP
                                              +-- U_VGA_SYNC both CP inputs

Two cascaded inverters give a non-inverting buffered copy. No motherboard clock net gains a load, so the clock distribution budget is unchanged.

Synthesizer Filters

The internal dual-frequency synthesizer needs one loop filter per clock. The CL-GD5428 is an N-WELL device, so the video filter returns to AVSS1 rather than AVDD1.

TRM appendix B17 gives the video filter values for an N-WELL device and notes that the 2.2 uF capacitor's polarity is reversed relative to the P-WELL arrangement. The data book requires the same pi topology at MFILTER but the copy of the ISA adapter schematic in the manual is withheld, so the memory filter here repeats the characterized video filter values. Measured MCLK jitter at the DRAM strobes is on the acceptance list.

Reset

The controller's RESET input, pin 41, is active high. One U_VGA_INV_B channel inverts PERIPH_RESET_n, which places the video subsystem in the peripheral reset domain alongside the MFP, MIDI, OPL3, RTC, and floppy. A processor RESET instruction therefore clears the controller and re-latches CF1 from the strap resistors, and firmware must set the video mode again afterwards.

VGA_RESET = NOT PERIPH_RESET_n

RESET must stay high for at least 12 MCLK periods, 291.5 ns at the strapped frequency, and firmware must not issue the first IOW* until 12 MCLK periods after it falls. A processor RESET instruction supplies about 12.4 us through the peripheral reset domain, and the power-on and manual reset pulses are far longer, so the pulse width is met by more than four orders of magnitude.

PERIPH_RESET_n is an open-collector net with a 1 kohm pull-up, so its release edge is RC-limited. The floppy controller takes the same signal through the same kind of plain inverter, and the release-edge check in Clock and Reset covers this input as well.

The controller's memory data pins float during reset so the CF1 pull-downs can be read. Straps need 2 ns of setup and 25 ns of hold around the falling edge, which static resistors satisfy.

9. Configuration EEPROM

U_VGA_CFG is an NM93C46N, a 1 Kbit serial EEPROM organized as 64 sixteen-bit words. It holds monitor timing and configuration data that must survive power-off. The controller reaches it through SR8, and the interface exists only in ISA bus mode.

ESYNC* and EVIDEO* are bidirectional. They are inputs during normal operation and become outputs carrying the serial clock and serial data when firmware sets SR8[4]. They therefore take 10 kohm pull-ups, R_VGA_ESYNC and R_VGA_EVIDEO, rather than a hard tie to +5 V. The pull-ups draw 0.5 mA against a 12 mA sink rating.

SR8[5] latches the levels present on those two pins before SR8[4] turns them into outputs, and the latched levels keep driving HSYNC, VSYNC, BLANK*, and P7..P0. Sync therefore continues uninterrupted while firmware talks to the EEPROM, and the MFP keeps receiving vertical retrace edges. Firmware that omits SR8[5] will blank the display.

R_VGA_EEDI, 10 kohm to +5 V, defines EEDI while the EEPROM output is high impedance. SR8[0] resets to zero, so chip select is low and the device ignores the pulled-up clock and data lines until firmware drives them.

The device needs 1 us of data setup and hold around each rising serial clock edge, 2 us of clock high and low time, 2 us before output data is valid, and 10 us after the last bit of a write. Firmware supplies all of these as software delays; no hardware sequencer is involved.

10. Video Output and Monitor Connector

DAC Reference

The palette DAC draws its full-scale reference through IREF, pin 78. Full-scale output current follows If = (63 / 30) x IREF. The reference design draws 6.7 mA, loads each analog output with 150 ohms on the board, and relies on the monitor's own 75 ohm termination for an effective 50 ohms.

D_VGA_REF is a TL431 wired as a shunt reference with its reference pin tied to its cathode, giving 2.495 V. R_VGA_REF supplies it with 1.5 kohms from +5 V, drawing 1.67 mA, and C_VGA_REF is a 0.1 uF bypass at the cathode. Q_VGA_IREF is a 2N3904 with its base at that node, its emitter to ground through R_VGA_IREF, and its collector on IREF.

R_VGA_IREF = 270 ohms, 1 percent
IREF  = (2.495 - Vbe) / 270 = 6.6 mA at Vbe = 0.7 V
If    = 2.1 x 6.6 mA = 13.9 mA
Vpeak = 13.9 mA x 50 ohms = 0.69 V

Peak white lands 10 mV below the 0.7 V VGA level. The residual error follows the transistor's base-emitter voltage, so R_VGA_IREF is the single component to adjust if a measured white level needs correcting.

Analog Filtering

Each of RED, GREEN, and BLUE takes a 150 ohm resistor to analog ground placed at the controller pin, then a pi filter of two 47 pF capacitors around a ferrite bead on the way to the connector. The source resistor sits as close to the controller as the layout allows so the analog output sees no unterminated stub.

Monitor Connector

J_VGA is a DE-15 receptacle at the board edge. The CL-GD5428 has no DDC engine, so the display data channel and monitor identification pins are unconnected.

The recommended part is the Amphenol L77HDE15SD1CH4FVGA, a right-angle through-hole high-density DE-15 receptacle with board locks. Any DE-15 receptacle with the same footprint and the pinout below is acceptable.

Sync polarity is programmable through the miscellaneous output register, and firmware sets it to match the mode it selects.

Unused Video Pins

No VESA feature connector is provided. P7..P0, DCLK, BLANK*, and OVRW are left open. EVIDEO* and EDCLK* stay high through their pull-ups, so P7..P0 and DCLK remain outputs and drive nothing.

11. Interrupts

VSYNC, pin 68, connects to the monitor and to MC68901 GPIP2. The MFP senses a programmed edge, so a push-pull source needs no inverter and no pull-up. Both edges occur once per frame, and firmware chooses one through the MFP active-edge register. The MFP assigns vector $42. See MC68901 MFP and Interrupts.

VSYNC is high impedance whenever ESYNC* is low. R_VGA_ESYNC holds ESYNC* high, and the SR8[5] latch keeps the internal enable high while the pin drives the configuration EEPROM clock, so the pin is an output at all times after reset.

The controller also has an IRQ output on pin 52 that asserts at the start of the bottom border under CR11 control. It duplicates what VSYNC already provides and would need a second GPIP input, so it has no board connection.

12. Firmware Contract

The bit-level register descriptions are in the technical reference manual. This section states only what the hardware requires.

1. Wait at least 292 ns after PERIPH_RESET_n releases before the first register write. Any reset path on this board exceeds that by a wide margin.
2. Unlock the extension registers by writing $12 to SR6 at $E603C4 and $E603C5. The extension registers are inaccessible until this is done.
3. Set GRB[5] to 1 for a 2 MiB address range, set GRB[0] to 0 so offset register 0 is always selected, and set SR7[7:4] to 1000. Only after this does the controller answer accesses in $800000-$9FFFFF.
4. Set the video mode, CRTC timing, sync polarity, clock synthesizer numerators and denominators, palette, and any BitBLT or hardware cursor state. All of it is firmware's responsibility because the machine has no x86 video BIOS to run.
5. Repeat every step above after each processor RESET instruction. The controller sits in the peripheral reset domain and loses all state.
6. Read and write registers at odd or even byte addresses freely. The byte-lane crossing is symmetric and the address of a byte is the same on both sides of the bus.
7. A 16-bit write to an index port is permitted. The controller expects the index on SD7..SD0 and the data on SD15..SD8, which after the lane crossing means a MC68EC000 word whose high byte is the index and whose low byte is the data.
8. Set SR8[5] before setting SR8[4] when using the configuration EEPROM, and clear them in the reverse order afterwards. Skipping the latch step blanks the display and stops the vertical retrace interrupt.
9. Preserve SR8[6] across every write to SR8. It also controls MCS16*.
10. Own the display-memory timing if SR1F[5:0] is used to change MCLK away from the strapped 41.16477 MHz.

13. Package and Pin Maps

CL-GD5428 Host Interface

CL-GD5428 Video, Clock, and Serial Pins

CL-GD5428 Display-Memory Pins

CL-GD5428 Power and Ground

TRM appendix B10 suggests feeding the logic supply through two 1 ohm resistors in parallel for extra latch-up margin. At the rated 260 mA that pair drops 130 mV, which would leave 4.62 V at the device when the rail sits at its 4.75 V minimum, below the controller's own 4.75 V floor. The logic supply therefore connects directly and relies on per-pin bypassing and the internal latch-up protection instead.

Adapter Packages

Every spare gate input ties to ground and every spare output is left open.

14. Timing and Electrical Checks

VGA_CLK_14 has a 69.83 ns period. The strapped MCLK has a 24.29 ns period. Every adapter interval below is a whole number of VGA_CLK_14 periods measured from the first rising edge after VGA_CYCLE asserts.

Completion Release

The MC68EC000FN10 requires /DTACK to negate within 110 ns of AS_n or the data strobes negating. VGA_DTACK_n releases through one SN74F04N inverter and one SN74F00N NAND driven directly from AS_n, so the path is two FAST gate delays and does not wait for the shift register to clear.

U_VGA_INV SN74F04, tPHL      5.3 ns maximum
U_VGA_NAND_B SN74F00, tPLH   6.0 ns maximum
group SN74F21, tPLH          5.3 ns maximum
final SN74F21, tPLH          5.3 ns maximum
timeout-mask SN74F32, tPLH   6.6 ns maximum
------------------------------------------------
component total             28.5 ns
MC68EC000 limit            110.0 ns
board allowance             81.5 ns

Cycle Length

Completion arrives 349.2 ns after VGA_CYCLE asserts. VGA_CYCLE is not phase-aligned with VGA_CLK_14, so the first clock edge falls anywhere in one period and completion lands between 349.2 ns and 419.0 ns after the qualifying strobe.

The MC68EC000 tests /DTACK at the falling edge of S4 and again once per clock period after that, needing 20 ns of setup. At 10 MHz the decision points fall 80, 180, 280, 380, and 480 ns after AS_n. A register access therefore takes three or four wait states, for a 500 to 600 ns cycle. Confirm the count on the assembled board.

A display-memory access adds however long the controller holds IOCHRDY low, which depends on the video mode and on contention with screen refresh, plus two synchronizer clocks. The motherboard's minimum 51.1 us timeout bounds it.

Loading

The CL-GD5428 specifies 10 pF maximum input and output capacitance. It adds one input to each of A23..A1, UDS_n, and LDS_n, and one bidirectional pin to each of D15..D0. Its SD15..SD8 pins carry internal pull-ups, which appear on CPU D7..D0 after the lane crossing. Recount the address, data, AS_n, and data-strobe capacitance with these loads included when the board is routed.

The controller-to-processor high margin is 0.40 V at its rated 400 uA source current, matching the firmware ROM case. Include every disabled output, receiver, and pull resistor when calculating load on the shared data bus.

Supply Current

The CL-GD5428 draws 260 mA at an 80 MHz video clock and a 50 MHz memory clock, and dissipates up to 1.5 W. Four 256K x 16 DRAMs, one 14.31818 MHz oscillator at up to 25 mA, and ten logic packages add to that. Fold the total into the board supply budget before layout.

15. Parts Added

16. Board Layout

• Place the CL-GD5428 160-pin PQFP footprint and the four DRAM footprints on the board. Mark pin 1 on copper and silkscreen for each.
• Follow the TRM placement order of controller, then display memory, keeping the display-memory bus short and matched across the four devices.
• Keep OSC at pin 159 and RESET at pin 41 as short as the layout allows, and route them away from the display-memory bus.
• Place R_VGA_CLK at the oscillator output and Y_VGA_CLK beside the controller.
• Place the VFILTER and MFILTER networks against pins 65 and 155, with the series resistor and the input capacitor closest to the pin. Lay out the video filter so it accepts either N-WELL or P-WELL capacitor polarity, and populate the N-WELL arrangement.
• Place the two 6.8 kohm CF1 straps at controller pins 100 and 104, away from DRAM data stubs.
• Place the 150 ohm source resistors against controller pins 75, 76, and 77, then the pi filters, then J_VGA.
• Isolate the connector chassis ground plane from digital ground and join it only at the J_VGA mounting holes.
• Keep the IREF reference circuit and its bypass away from the display-memory bus and the DAC outputs.
• Choose the J_VGA board-edge position and the exact receptacle part, and label the connector.
• Give each of the seven VDD pins its own 0.1 uF bypass at the pin and connect all thirteen VSS pins directly to the ground plane.
• Isolate RESET and IOCHRDY from the high-speed data lines with a ground trace.
• Measure VGA_CLK_14 at controller pin 159 and confirm frequency within 100 parts per million and duty cycle between 40 and 60 percent, both of which sit exactly at the controller's limit.
• Measure BALE, all four command strobes, IOCHRDY, and VGA_DTACK_n at their receiving pins. Keep the routed VGA_DTACK_n release contribution below 81.5 ns.
• Measure MCLK jitter and all four DRAM strobes at the DRAM pins, since the memory loop filter values are inferred from the video filter.
• Include the CL-GD5428 in the address, data, and data-strobe capacitance budgets.
• Add the video subsystem to the +5 V supply budget, including the 260 mA controller rating.
• Measure peak white at J_VGA pins 1, 2, and 3 with a monitor connected and adjust R_VGA_IREF if it falls outside 0.7 V by more than the monitor tolerates.

17. Assembled-System Acceptance

1. With the board reset and no firmware writes, confirm VGA_RESET follows PERIPH_RESET_n and that MD28 and MD25 sit below 0.8 V while RESET falls.
2. Read CR27, the ID register, through $E603D4 and $E603D5 and confirm the controller answers.
3. Write and read back a scratch pad register, SR9 at $E603C4 and $E603C5, after unlocking with SR6 = $12. Confirm the byte survives.
4. Confirm a read of $800000 before linear addressing is enabled returns without asserting /BERR, then enable GRB[5] and SR7[7:4] and confirm the same address now stores and returns a written pattern.
5. Write a unique byte to the first and last address of each 256 KiB block across $800000-$9FFFFF and read them all back. Every location must be distinct, which proves the full 2 MiB is present and unaliased.
6. Write a word to display memory and read back both bytes individually. Confirm the even byte matches D15..D8 of the word and the odd byte matches D7..D0.
7. Capture IOCHRDY and VGA_DTACK_n during a display-memory read and confirm completion follows the rising IOCHRDY edge by two adapter clocks.
8. Confirm VGA_DTACK_n releases within 110 ns of AS_n rising.
9. Write a configuration EEPROM word and read it back after a power cycle. Confirm the display stays lit and the MFP keeps receiving GPIP2 edges throughout the transfer.
10. Enable the vertical retrace interrupt at the MFP and count edges on GPIP2. The rate must match the programmed vertical frequency.
11. Issue a processor RESET instruction and confirm the controller blanks, re-latches CF1, and comes back after firmware repeats its initialization.
12. Display a full-screen white field and measure the analog outputs at the connector with a monitor attached.
13. Run the board for an hour at the highest mode firmware supports and confirm the display memory still passes the pattern test.

18. Internal Signal Reference

19. Sources

• Cirrus Logic, CL-GD542X True Color VGA Family Preliminary Data Book, version 7.0. Pin diagram and descriptions, ISA host timing, configuration register CF1, DC specifications, reset timing, and the VGA register port map.
• Cirrus Logic, CL-GD542X Technical Reference Manual. Extension register definitions for SR6, SR7, SR8, SR1F, and GRB; appendix B1 for the ISA reference design and the IREF circuit; appendix B7 for display-memory configurations; appendix B8 and B19 for MCLK selection and DRAM timing; appendix B10 for layout; appendix B15 for the configuration EEPROM; and appendix B17 for the N-WELL video clock filter.
• Epson, SG-615, SG-531, and SG-51 Series. Reference oscillator; frequency tolerance, symmetry, output levels, and load conditions.
• Texas Instruments, TL431 Precision Programmable Reference. Reference voltage and minimum cathode current for the DAC current sink.
• Texas Instruments, CD74HCT164, SN74HCT74, and the local FAST logic data sheets (F00, F02, F04, F08, F32). Adapter pinouts, thresholds, and propagation delays.
• Motorola, M68000 User's Manual. Byte-lane selection, read and write cycle timing, and /DTACK negation requirements.