Interrupts

1. Purpose and Scope

This document defines how the motherboard presents interrupt requests to the MC68EC000 and how it terminates the processor's interrupt-acknowledge cycle. It covers priority encoding onto /IPL2../IPL0, acknowledge-cycle decode, autovector generation, the MC68901 MFP vectored acknowledge, routing of peripheral interrupt outputs, and spurious-interrupt handling.

Device register maps, internal interrupt-enable and mask registers, and adapter timing stay in the individual device documents. This page owns only the CPU-facing interrupt hardware and the wiring between the devices' interrupt outputs and that hardware.

A signal ending in _n, or written with a leading slash, is active low: 0 means asserted and 1 means inactive. Interrupt levels are the processor priority levels 1 through 7.

Inputs this page takes from other documents:

CPU_SPACE      active-high CPU-space decode      Bus and Decode (U_AND)
AS_n           processor address strobe          MC68EC000
A1, A2, A3     acknowledged interrupt level      MC68EC000
A16..A19       CPU-space type field (all high)   MC68EC000
INT_CLK        buffered 10 MHz, spare U_DRAM_CLK_BUF channel   DRAM
RESET_n        conditioned board reset           Clock and Reset
PERIPH_RESET_n processor-honoring peripheral reset             Clock and Reset
D7..D0         lower data byte, vector transfer  MC68EC000

Outputs this page drives:

/IPL2, /IPL1, /IPL0   encoded interrupt priority    MC68EC000 inputs
/AVEC                 autovector request           MC68EC000 input
INT_BERR_n           spurious-acknowledge abort    into the CPU /BERR path

2. MC68EC000 Interrupt Model

The processor samples three encoded priority inputs and compares the requested level against the interrupt mask in the status register. A request at a level above the mask starts exception processing at an instruction boundary. Level 7 is compared as an edge and cannot be masked.

Priority Encoding

/IPL2../IPL0 carry the requested level as the one's complement of the binary level number, with /IPL2 most significant. All three high means no request.

A request must stay asserted until the processor acknowledges it. The interrupt sources used here are level-held until their controller is serviced, which satisfies this rule.

Acknowledge Cycle

When the processor grants an interrupt it runs a CPU-space read cycle: FC2..FC0 = 111, A19..A16 = 1111, all other address lines high, and A3..A1 holding the level being acknowledged. The cycle ends one of three ways.

/DTACK and /AVEC must never be asserted in the same acknowledge cycle.

Vector Address Table

A vector number is multiplied by four to form the exception-vector address. After the boot overlay is disabled the vector table lives in DRAM bank 0; see Memory Map and Firmware ROM.

Source: M68000 User's Manual, sections 5.1.4, 6.2, and 6.3.4.

3. Architecture Overview

One device, the MC68901 MFP, acts as the system interrupt controller. It has sixteen internal channels with their own priority, enable, mask, pending, and in-service registers, and it produces a full vector number during its acknowledge cycle. Slow or infrequent peripheral interrupts feed the MFP's general-purpose I/O interrupt inputs rather than consuming a processor level.

Only two other processor levels are used: level 3 for the expansion-bus request and level 7 for the manual non-maskable interrupt. Both are autovectored and served by reading device status in software. Levels 1, 2, 4, and 5 carry no source.

            MFP /IRQ ---------------------+
 EXP_IRQ_n --------------------------+     |
 NMI_n -----------------------+      |     |
                              |      |     |
              level 7 --------+      |     |
              level 3 ---------------+     |
              level 6 ---------------------+
                              |      |     |
                              v      v     v
                        +--------------------------+
                        |  U_IPL_ENC   74LS148     |   I1..I7 = levels
                        +------------+-------------+
                                     | A2..A0
                                     v
                        +--------------------------+
                        |  U_IPL_SYNC  74LS174 x2  |   two stages on INT_CLK
                        +------------+-------------+
                                     v
                        /IPL2  /IPL1  /IPL0  ->  MC68EC000

 CPU_SPACE, AS_n, A16..A19 --> IACK qualifier --> U_IACK_DEC 74HCT138
                                                   |  IACK_L1_n .. IACK_L7_n
                    +------------------------------+------------------+
                    v                              v                  v
           autovector OR (U_AVEC_OR)      IACK_L6_n -> MFP /IACK   watchdog
                    |                              |  MFP D7..D0 + /DTACK   (U_INT_WDOG)
                    v                              v                  v
                  /AVEC -> CPU               MFP_DTACK_n         INT_BERR_n
                                             -> completion tree  -> CPU /BERR

 INT_CLK = spare U_DRAM_CLK_BUF channel off DRAM_CLK_10 (see dram.html)

4. Interrupt Level Assignment

Sources folded into the MFP instead of a processor level: the 82077AA-1 floppy INT, the MC6850 MIDI /IRQ, and the DS1285 RTC /IRQ. They use GPIP5, GPIP4, and GPIP3 respectively. See the MFP channel map and section 9.

The video controller has no processor-level interrupt. MFP Timer C generates the nominal 100 Hz system tick, and the CL-GD5428 VSYNC output connects to MFP GPIP2. Both inherit the MFP's masking and vectoring.

5. Priority Encoding and /IPL Generation

U_IPL_ENC, a SN74LS148 8-line-to-3-line priority encoder, converts up to seven level requests into the /IPL code. Its active-low outputs already carry the one's complement of the highest requested input, which matches the /IPL encoding directly.

The SN74LS148 is the practical choice: neither an HCT nor a current HC version of the 148 is available. The LS part is fast and widely stocked. It and the SN74LS174 synchronizer that follows are both LS-family, so the encoder outputs drive the register inputs at TTL levels with no translation. Encoder propagation delay does not matter because U_IPL_SYNC reclocks the output.

An unwired input is tied to +5 V so it never requests. Only /I3, /I6, and /I7 take a source in this design; the other four inputs are held inactive.

Synchronizer

The encoded outputs are asynchronous to the processor clock because MFP_IRQ_n, EXP_IRQ_n, and the MFP's own wired-OR inputs change at arbitrary times. U_IPL_SYNC is two register stages, one SN74LS174 hex D flip-flop per stage using three of six flip-flops, both clocked by INT_CLK. It registers all three encoded bits together so a change near a sampling edge cannot present an inconsistent code.

on each rising INT_CLK edge:
  s1[2:0] <- IPL_ENC2..0_n
  s2[2:0] <- s1[2:0]

/IPL2../IPL0 = s2[2:0]

A held request reaches the processor after at most two INT_CLK periods, far below any interrupt service interval. The level-7 edge is delayed, not lost. The MC68EC000 also samples /IPL over consecutive cycles internally, so a single external stage would deglitch the code; the second stage is margin against metastability propagation and can be dropped after review.

INT_CLK is a buffered copy of the 10 MHz processor clock. Any buffered copy works; a direct tap on the processor clock net is a poor choice because that net is usually already near its capacitive budget. This design takes INT_CLK from a spare channel of the DRAM clock buffer; see dram.html and section 16. The SN74LS174 common clear is tied inactive: clearing would force the encoded code to 000, which is level 7. Instead, two INT_CLK edges after reset release load the true no-request code, which is harmless because the processor mask is 7 during that interval.

6. Interrupt Acknowledge Decode

On the MC68EC000 the only CPU-space cycle is an interrupt acknowledge, so CPU_SPACE asserted with AS_n low already identifies an acknowledge. The address type field A19..A16 is decoded as well so a future non-acknowledge CPU-space cycle cannot be mistaken for one.

IACK_TYPE   = A16 AND A17 AND A18 AND A19        4-input AND
IACK_ACTIVE = CPU_SPACE AND (NOT AS_n) AND IACK_TYPE
IACK_n      = NOT IACK_ACTIVE

IACK_TYPE uses one gate of a CD74HCT21 4-input AND (U_IACK_QUAL); its second gate is spare. IACK_ACTIVE and IACK_n use a SN74HCT08 gate and an inverter in U_INT_GATE. Pin-level gate packing is fixed at schematic capture.

Level Demultiplex

U_IACK_DEC, a SN74HCT138 3-line-to-8-line decoder, splits the acknowledge into one active-low strobe per level using the level on A3..A1.

A0 is high during the acknowledge and is not decoded. The decoder mirrors nowhere because it is enabled only by IACK_n.

7. Autovector Generation

For every level served by autovector, the corresponding IACK_Lx_n strobe drives /AVEC low. U_AVEC_OR combines the active autovector strobes.

AVEC_n = IACK_L3_n AND IACK_L7_n
/AVEC  = AVEC_n

The equation is an AND of active-low strobes: either the level-3 or the level-7 acknowledge pulls /AVEC low. Levels 1, 2, 4, and 5 are not included; an acknowledge to any of them falls through to the spurious path in section 10, which treats an unwired level as a hardware fault. U_AVEC_OR is one gate of a SN74HCT08 AND package.

/AVEC is combinational from the decoder, so it is valid well before the processor samples it at the falling edge of S4. It is released when AS_n negates and the decoder outputs go inactive.

8. MFP Vectored Acknowledge

Level 6 belongs to the MC68901 MFP. The MFP holds sixteen prioritized interrupt channels and, during its acknowledge cycle, drives an 8-bit vector number onto D7..D0 and asserts its own /DTACK.

The MFP asserts /DTACK both for ordinary register accesses and for the vectored acknowledge. Its physical output is MFP_DTACK_n, one of the normal completion-tree inputs. The tree remains active during CPU space, so the same net terminates a level-6 acknowledge. IO0_n is inactive during CPU space, which keeps /CS high while /IACK is low.

MFP /DTACK pin = MFP_DTACK_n -> U_DTACK_A gate 1 -> completion tree

normal register cycle: /CS low, /IACK high
level-6 acknowledge:   /CS high, /IACK low

Vector Register

The MFP vector register holds the upper nibble of the vector; the MFP fills the lower nibble with the channel number during acknowledge, and bit 3 of the register selects software or automatic end-of-interrupt mode. Firmware programs the base to $40, placing the sixteen MFP vectors at numbers $40-$4F (addresses $000100-$00013C), clear of the autovector and processor-defined ranges.

MFP vector number = $40 | channel[3:0]

The complete channel-to-vector map is in the MFP document.

9. Peripheral Source Routing

Peripheral interrupt outputs that do not have their own processor level connect to the MFP's general-purpose interrupt inputs. The MFP gives each one a channel priority, an enable bit, a mask bit, and a vector.

Each open-drain interrupt output gets a 4.7 kohm pull-up to +5 V at its receiver. That sinks about 1 mA, within an open-drain output's rating alongside the SN74LS148 input current on the encoder lines, and releases quickly given the small wired-OR count. Size the pull-up down toward 3.3 kohm if a line gathers more loads or needs a faster release; confirm the final value against trace capacitance and load count on the assembled board.

The MFP general-purpose interrupt inputs sense a programmed edge set in the active-edge register, so a push-pull active-high source and an open-drain active-low source both connect directly with no inverter; firmware sets the matching edge. This is a device-configuration detail; see mfp.html.

The MFP GPIP map also assigns GPIP7 and GPIP1 to the PS/2 keyboard, GPIP6 and GPIP0 to RS-232 flow control, and GPIP2 to VGA vertical sync. All eight pins have fixed board connections.

The YMF262 OPL3 does not consume an interrupt input. Firmware reads its timer flags through OPL3 port 0, and the YMF262 /IRQ pin has no board connection.

10. Spurious and Phantom Acknowledge Termination

The motherboard bus timeout is disabled during CPU space, so an acknowledge cycle that no source terminates would stall the processor forever. This logic terminates every acknowledge that is not answered by /AVEC or MFP_DTACK_n.

Unwired Levels

An acknowledge to a level with no source and no autovector wiring (levels 1, 2, 4, and 5) is terminated immediately.

UNWIRED_IACK_n = IACK_L1_n AND IACK_L2_n AND IACK_L4_n AND IACK_L5_n

UNWIRED_IACK_n is one gate of a CD74HCT21 4-input AND. When any of those strobes is low it goes low and drives INT_BERR_n low without waiting.

Phantom Acknowledge Watchdog

A wired level can still fail to respond: an interrupt withdrawn after the processor has latched the level, or an MFP caught between states. U_INT_WDOG, a CD74HCT4040E ripple counter, counts INT_CLK edges while an acknowledge is unanswered and asserts INT_BERR_n when the count is reached.

ANSWERED       = (NOT AVEC_n) OR (NOT MFP_DTACK_n)   any legitimate termination
WDOG_COUNT_EN  = IACK_ACTIVE AND AVEC_n AND MFP_DTACK_n
WDOG_MR        = NOT WDOG_COUNT_EN                   active-high counter reset
WDOG_TIMEOUT_n = NOT Q5                              Q5 = 32 counted INT_CLK edges
INT_BERR_n     = UNWIRED_IACK_n AND WDOG_TIMEOUT_n

The count is Q5, 32 INT_CLK periods, about 3.2 us. That is comfortably past the longest MC68901 acknowledge latency, still about sixteen times shorter than the 51.1 us normal bus timeout, and far below any software concern. If a measured MFP acknowledge is unexpectedly slow, Q6 (6.4 us) is the next tap; Q4 (1.6 us) is the tighter one.

WDOG_COUNT_EN is a three-input AND, WDOG_MR its inversion, and WDOG_TIMEOUT_n an inverter on Q5, all in U_INT_GATE.

Motherboard Bus Error

INT_BERR_n is combined with the motherboard TIMEOUT_BERR_n in Bus and Decode, in a spare gate of the CPU-space AND package:

BERR_n = TIMEOUT_BERR_n AND INT_BERR_n

Either source pulls the processor /BERR input low. The two are mutually exclusive in time because the bus timeout does not run during CPU space.

A spurious termination leaves /HALT inactive, so the processor takes the spurious-interrupt exception (vector 24) rather than a double bus fault.

11. NMI and Level 7

Level 7 cannot be masked. The processor takes a level-7 interrupt on every transition of the request level from below 7 up to 7, so a held request produces exactly one interrupt.

The source is one momentary pushbutton to ground near the debug display, with a pull-up and an SN74LS14 Schmitt-trigger conditioner, the same pattern the manual-reset input uses. The conditioned output is NMI_n, wired to U_IPL_ENC /I7.

The specified switch is the C&K FP11SPC1B1TP00, the same normally-open momentary SPST pushbutton used for the front-panel power and reset buttons.

button --- RC --- SN74LS14 stage --- gate with RESET_n --- NMI_n --- U_IPL_ENC /I7

12. Reset Behavior

After RESET_n:

• The MFP is reset through PERIPH_RESET_n (Clock and Reset). All MFP channels are disabled and /IRQ is negated, so U_IPL_ENC /I6 is inactive.
• NMI_n is held inactive while RESET_n is low, so a button press during reset is ignored.
• With every encoder input inactive, /IPL2../IPL0 reads 111 (no request).
• U_INT_WDOG is held reset by WDOG_MR because no acknowledge is active. No separate RESET_n term is needed.
• U_IPL_SYNC is not cleared on reset, since clearing it would encode level 7. Its two INT_CLK edges after reset release load the true no-request code. During that interval the processor mask is 7 and no interrupt is taken, so the transient is harmless.
• The processor sets its interrupt mask to 7 on reset, so no autovectored or vectored interrupt is taken until firmware lowers the mask. Firmware initializes the exception vectors in low RAM first; see Firmware ROM.

13. Acknowledge Timing

The acknowledge cycle is a normal-length MC68EC000 read cycle, four clock periods plus wait states, terminated by /AVEC, by the MFP vector and MFP_DTACK_n, or by INT_BERR_n. Use the 10 MHz column of M68000 User's Manual, section 10.14, together with the interrupt-acknowledge timing in the manual's section 5.

A worked assertion and release budget for each termination path, in the style of the Firmware ROM read timing tables, is added once package pins and gate packing are set at schematic capture. The dominant unknown is the MC68901 acknowledge latency, which is a measurement.

There is no motherboard bus timeout on this cycle. The only backstop is INT_BERR_n from this logic.

14. Motherboard Integration

Four signals connect the interrupt controller to the bus and clock circuits. The Bus and Decode and DRAM documents carry the matching connections.

This logic also adds one input load to CPU_SPACE and AS_n, and one to each of CPU address lines A1..A3 and A16..A19. These belong in the bus fanout budget.

15. Package and Pin Map

Reference designators and parts. Package pin numbers and the gate assignment within the multi-gate packages follow from the schematic; the equations in the sections above define the logic.

Every package gets a 100 nF bypass capacitor at its supply pins, and U_INT_WDOG and the two synchronizer packages also get a 1 uF capacitor in parallel, per the motherboard convention.

16. Electrical and Fanout

All parts run from the regulated 5 V +/-5% rail and use TTL-compatible thresholds.

17. Design Notes

Why the design is shaped this way, for anyone adapting it.

The MFP design fixes the GPIP assignments, a 2.5 MHz MFP clock, 4.7 kohm open-drain pull-ups, and the direct MFP_DTACK_n completion path. The MC68901's worst-phase acknowledge response fits inside the 3.2 us Q5 watchdog interval. Board layout must preserve the acknowledgement timing limits in section 13.

18. Internal Signal Reference

Names ending in _n are active low. Others are active high unless the description says otherwise.

19. Sources

M68000 User's Manual: section 3.5 (interrupt control inputs), section 5.1.4 (CPU space cycle), section 5 interrupt-acknowledge timing (Figure 5-11), section 6.2 (exception vectors), section 6.3.3 to 6.3.5 (uninitialized, spurious, and instruction traps), and the section 10.14 MC68EC000 10 MHz switching table.

MC68901 MFP: interrupt controller registers, the /IACK / IEI / IEO daisy chain, the vector register, general-purpose interrupt inputs and the active-edge register, and /DTACK generation.

Devices

Related project documents: Bus and Decode (CPU-space decode, completion tree, bus error), MFP (channel map, GPI assignments, vector base), DRAM (INT_CLK spare clock-buffer channel), Clock and Reset (RESET_n, PERIPH_RESET_n, Schmitt conditioning), Memory Map and Firmware ROM (vector table location and initialization), Expansion Bus (EXP_IRQ_n), and Floppy, MIDI, RTC, and VGA for their interrupt outputs.