YMF262 OPL3

1. Purpose and Scope

The YMF262 supplies 18 two-operator voices, up to six four-operator voices, five rhythm sounds, eight waveforms, two timers, and four selectable output channels. Two YAC512 converters turn its serial output into channels A through D. The motherboard mixes A with C for the left ear and B with D for the right ear, then drives a 3.5 mm stereo jack through a dual headphone amplifier.

The Memory Map owns I/O slot 2 and the canonical port addresses. Bus and Address Decode owns IO2_n, the completion tree, and timeout behavior. The Clock and Reset design owns PERIPH_RESET_n. This page owns the dedicated clock, reset stretcher, bus response, conversion, mixing, and output circuits.

Signal names ending in _n, and names written with a leading slash, are active low. Logic uses +5 V. The headphone stage uses +12 V. ICs use through-hole packages except the YMF262-M and two YAC512-M devices, which have no DIP version and mount directly to the motherboard. Every IC family selected here existed before 1994.

2. Architecture

MC68EC000 lower byte                    YMF262-M

D7..D0 <----------------------------> D7..D0
A1 ----------------------------------> A0
A2 ----------------------------------> A1
IO2_n + LDS_n --> OPL3_CYCLE --------> request synchronizer
AS_n --> inverter -------------------> adapter state hold
OPL3_CLK_14 --> counter and state ---> /CS, /RD, /WR
adapter completion ------------------> OPL3_DTACK_n
PERIPH_RESET_n --> reset stretcher --> /IC

Y_OPL_CLK 14.31818 MHz --------------> OPL3_CLK_14

YMF262-M                              two YAC512-M converters

DOAB -------------------------------> DAC_AB DIN --> channels A and B
DOCD -------------------------------> DAC_CD DIN --> channels C and D
phiSY ------------------------------> both DAC CLK inputs
SMPAC ------------------------------> both DAC SMP1 inputs
SMPBD ------------------------------> both DAC SMP2 inputs

A -- filter --+
              +-- left mix -- volume -- NJM4556AD -- tip
C -- filter --+

B -- filter --+
              +-- right mix - volume -- NJM4556AD -- ring
D -- filter --+

audio ground ------------------------------------------- sleeve

The bus adapter runs from the YMF262 master clock. Reads wait for valid status data. Writes end after four counter clocks, but the CPU remains stopped until 64 counter clocks have elapsed. The next access cannot violate the YMF262's 32-clock write-recovery rule.

3. Bus Interface

Cycle Qualification

U_OPL_REQ, one SN74F02N gate, asserts OPL3_CYCLE only while slot 2 and the lower byte lane are selected.

OPL3_CYCLE = NOT (IO2_n OR LDS_n)

Upper-byte accesses reach the motherboard timeout. A word access completes through its lower lane, but only D7..D0 carry OPL3 data. Firmware shall use byte accesses at odd addresses. Address lines A16..A3 are not decoded, so the eight-byte pattern repeats through the slot.

Valid Operations

All four ports accept writes. Only port 0 supports a read. Reads from ports 1 through 3 are withheld from the YMF262 and end through the normal bus timeout, avoiding an undefined device-bus mode.

OPL3_STATUS_ADDRESS = NOT (A1 OR A2)
OPL3_READ_CYCLE = OPL3_CYCLE AND R/W AND OPL3_STATUS_ADDRESS
OPL3_WRITE_CYCLE = OPL3_CYCLE AND NOT R/W

4. Bus Adapter and Write Recovery

U_OPL_SYNC is an SN74HCT74N. Its first half samples OPL3_CYCLE on each rising OPL3_CLK_14 edge; its second half samples the first output. Both active-low clears connect to OPL3_AS_ACTIVE, the inverse of AS_n. Raising AS_n clears the request without waiting for a clock edge.

U_OPL_COUNT is a CD74HCT4040E. U_OPL_INV holds its master reset high until OPL3_REQ_SYNC asserts. The counter then advances on falling clock edges. Q3 rises after four falling edges and Q7 rises after 64.

U_OPL_STATE is a second SN74HCT74N. Its first half clocks from Q3 and records OPL3_STROBE_DONE. Its second half clocks from Q7 and samples OPL3_WRITE_CYCLE to produce OPL3_WRITE_DONE. Both halves clear while OPL3_REQ_SYNC is low.

OPL3_AS_ACTIVE = NOT AS_n
OPL3_READ_QUALIFIER = R/W AND OPL3_STATUS_ADDRESS
OPL3_READ_STROBE = OPL3_REQ_SYNC AND OPL3_READ_CYCLE

OPL3_WRITE_STROBE =
    OPL3_REQ_SYNC AND OPL3_WRITE_CYCLE AND NOT OPL3_STROBE_DONE

OPL3_RD_n = NOT OPL3_READ_STROBE
OPL3_WR_n = NOT OPL3_WRITE_STROBE
OPL3_CS_n = NOT (OPL3_READ_STROBE OR OPL3_WRITE_STROBE)

OPL3_READ_DONE = OPL3_READ_QUALIFIER AND OPL3_STROBE_DONE
OPL3_ACK_READY = OPL3_READ_DONE OR OPL3_WRITE_DONE
OPL3_DTACK_n = NOT (OPL3_AS_ACTIVE AND OPL3_ACK_READY)

At 14.31818 MHz, four periods are 279.4 ns and 64 periods are 4.469 us. The interval from Q3 to Q7 is 60 clocks, safely beyond the required 32 clocks. The slower write response remains far inside the motherboard's 51.1 us minimum timeout.

Gating completion with OPL3_AS_ACTIVE keeps OPL3_DTACK_n low if the CPU releases LDS_n before AS_n. It releases completion when AS_n rises.

5. Ports and Register Groups

Yamaha's non-linear operator table assigns the addresses within the operator ranges. Firmware shall use that table rather than treating the ranges as contiguous voice records.

6. Clock and Reset

Dedicated Master Clock

Y_OPL_CLK is a packaged 14.31818 MHz clock oscillator. Any oscillator meeting the specification below is acceptable. The Epson SG-615 series is the reference part and the source of the output levels checked below; the ECS ECS-100AX-143 is an equivalent alternative if the Epson part cannot be sourced. Its output reaches YMF262 pin 24 through R_OPL_CLK, a 33 ohm source-series resistor. Oscillator enable is tied high. No other subsystem uses OPL3_CLK_14.

The nominal sample rate is 49.716 kHz because the YMF262 divides its clock by 288. The oscillator's CMOS output meets the YMF262 clock input's 3.5 V high threshold.

Reset Stretcher

The YMF262 requires /IC low for at least 400 clock periods, or 27.94 us at the nominal frequency. A CPU RESET instruction holds PERIPH_RESET_n low for about 12.4 us, so a direct connection is too short.

U_OPL_RESET is one half of a CD74HCT123E. Its /A input is grounded, B is high, and /CLR receives PERIPH_RESET_n. R_OPL_RESET is 100 kohms and C_OPL_RESET is 100 nF, producing a nominal 4.5 ms pulse from tW = 0.45RC. U_OPL_RESET_GATE combines the incoming reset with the complementary pulse output.

OPL3_IC_n = PERIPH_RESET_n AND OPL3_RESET_PULSE_n

The unused monostable half has /CLR grounded and fixed trigger inputs. Reset clears every YMF262 register.

7. Firmware Contract

1. Wait for OPL3_IC_n release before the first access.
2. Write $05 to port 2, then $01 to port 3 to enable OPL3 operation.
3. Program operators, channels, and routing before setting key-on.
4. Route voices to A and C for left output and B and D for right output.
5. Write a register number to its address port, then its value to the matching data port. Hardware supplies the recovery delay.
6. Poll port 0 for timers. Bit 7 is the combined request, bit 6 is timer 1 overflow, and bit 5 is timer 2 overflow.
7. Reset timer flags through array-0 register $04. The physical /IRQ pin is unused.

8. YAC512 Interface

U_OPL_DAC_AB and U_OPL_DAC_CD are YAC512-M two-channel floating converters. Both FSEL pins connect to +5 V for offset-binary input. Both CLK pins receive YMF262 phiSY.

This is Yamaha's second connection example. Each converter follows Yamaha's sample circuit. CV has 10 uF to ground and drives MP through a unity-gain NJM4560D section. Another section returns AOUT to SWIN through 33 ohms; 47 pF connects from AOUT to the amplifier output. CH1 and CH2 each have 2700 pF to ground and a unity-gain buffer.

Two NJM4560D packages serve each converter. The four packages run from AUDIO_5V and AUDIO_NEG_5, keeping the 2.5 V converter center voltage inside their input and output ranges.

9. Filtering and Stereo Mixing

Each buffered channel passes through 3.3 kohms to a 2.2 nF capacitor to ground. This 21.9 kHz single-pole filter reduces sampling energy. A 1 uF film capacitor then removes the converter bias.

DAC A -- 3.3k --+-- 1uF -- 47k --+
                |                 |
               2.2nF              +-- VOLUME_L high terminal
                |                 |
               GND                |
                                  |
DAC C -- 3.3k --+-- 1uF -- 47k --+
                |
               2.2nF
                |
               GND

DAC B and DAC D use the same network for VOLUME_R.

RV_OPL_VOLUME is a dual-gang 10 kohm logarithmic potentiometer. Its low terminals connect to audio ground. Each wiper feeds one headphone channel through 2.2 uF. The 47 kohm summing resistors prevent one DAC channel from driving another.

The recommended part is the Bourns PDB182-K415K-103A1, a dual-gang 10 kohm audio-taper panel potentiometer. Any dual-gang 10 kohm logarithmic potentiometer with the same footprint is acceptable.

10. Headphone Output

U_OPL_HP is an NJM4556AD dual high-current amplifier on AUDIO_12V and ground. Two 10 kohm resistors create OPL3_AUDIO_BIAS at half supply; 100 uF and 100 nF bypass that node.

Each channel is non-inverting. A 100 kohm resistor biases its positive input. A 10 kohm resistor from the negative input to the bias node and a 10 kohm feedback resistor set gain to two. Each output reaches the jack through 470 uF, positive terminal toward the amplifier, followed by 10 ohms.

The recommended jack is the Same Sky SJ1-3535N, a through-hole 3.5 mm stereo switched jack. Any 3.5 mm TRS jack with the same footprint and the contact assignment below is acceptable.

The 10 ohm resistors isolate cable capacitance and limit fault current. The intended load is 32 ohms or higher. The AC-coupled output can also feed a line input at a reduced volume setting.

11. Power and Grounding

Converter Supplies

FB_OPL_5V feeds AUDIO_5V from +5 V. The YAC512 VDD pins and NJM4560D positive-supply pins use this rail. Each supply pin has 100 nF, and each converter has 10 uF beside the package. The YMF262 and bus adapter remain on the logic rail.

U_OPL_NEG is an LT1054CN8 data-sheet voltage inverter. A 10 uF flying capacitor connects CAP+ to CAP-, 2.2 uF bypasses VCC, and 100 uF connects VOUT to ground with its positive terminal at ground. FB/SHDN and OSC remain open.

Ten ohms separates VOUT from AUDIO_NEG_5. A 470 uF capacitor, positive terminal at ground, and 100 nF bypass the filtered rail. Only the four NJM4560D packages use it. Their load remains below the LT1054's 100 mA rating.

Headphone Supply

FB_OPL_12V feeds AUDIO_12V from +12 V. A 470 uF electrolytic and 100 nF ceramic capacitor sit beside U_OPL_HP. Audio returns join the continuous ground plane in the audio area. There is no isolated audio ground.

12. Package and Pin Maps

YMF262-M

YAC512-M

Adapter and Analog Packages

13. Timing and Electrical Checks

Completion Release

The MC68EC000FN10 requires /DTACK to negate no later than 110 ns after AS_n or the data strobes negate. OPL3_DTACK_n releases from AS_n alone, through the U_OPL_INV inverter and the U_OPL_ACK NAND, without waiting for the counter or the state registers. Release is a rising edge at every node after the inverter.

U_OPL_INV SN74F04, tPHL      5.3 ns maximum
U_OPL_ACK SN74F00, tPLH      6.0 ns maximum
group SN74F21, tPLH          5.3 ns maximum
final SN74F21, tPLH          5.3 ns maximum
timeout-mask SN74F32, tPLH   6.6 ns maximum
------------------------------------------------
component total             28.5 ns
MC68EC000 limit            110.0 ns
board allowance             81.5 ns

Loading

The YMF262 adds one CMOS load to each lower-byte bus line. The local oscillator adds no motherboard clock load. U_OPL_RESET and U_OPL_RESET_GATE add two HCT inputs to PERIPH_RESET_n.

14. Parts Added

The YMF262 and YAC512 were sold as an OPL3 pair before 1994. Their SOP packages are exceptions to the through-hole IC rule. Yamaha's period YAC512 circuit names the NJM4560. The NJM4556A, LT1054, HCT, and FAST families also predate 1994. All other ICs use DIP packages. Each IC has a 100 nF ceramic bypass capacitor at its supply pins.

15. Board Layout

• Place the YMF262 and YAC512 SOP footprints directly on the board. Mark pin 1 on copper and silkscreen.
• Place Y_OPL_CLK beside YMF262 pin 24 and R_OPL_CLK at the oscillator output.
• Keep DOAB, DOCD, phiSY, SMPAC, and SMPBD short and away from headphone and volume traces.
• Copy the two YAC512 support networks symmetrically. Put each 2700 pF capacitor at its channel pin.
• Place U_OPL_NEG and its capacitors away from DAC outputs. Keep the 25 kHz switching loop compact.
• Keep CPU bus and 14.31818 MHz traces out of the analog area.
• Put RV_OPL_VOLUME and J_OPL_AUDIO at the selected board edge. Mark volume direction and label the jack HEADPHONES.
• Match left and right placement from the summing resistors through the jack.
• Place the 470 uF output capacitors and 10 ohm resistors beside the jack. Mark capacitor polarity.
• Join audio returns to the ground plane without a narrow shared path carrying charge-pump or digital current.
• Measure OPL3_CLK_14 at pin 24 and verify frequency, duty cycle, and monotonic edges.
• Measure all three YMF262 strobes and OPL3_DTACK_n at their receiving pins. Keep the routed OPL3_DTACK_n release contribution below 81.5 ns.
• Include the YMF262 in lower-byte bus capacitance and both reset-adapter inputs in the peripheral-reset load.
• Measure AUDIO_NEG_5 ripple under the four-buffer load.
• Measure DC at tip and ring before connecting headphones. Each contact must settle below 50 mV.

16. Assembled-System Acceptance

17. Internal Signal Reference

18. Sources

• Yamaha, YMF262 FM Operator Type L3. CPU interface, registers, serial output, clock, reset, and timing.
• Yamaha, YAC512 2-Channel Floating D/A Converter. Pinout, YMF262 connection, sample circuit, and analog limits.
• Epson, SG-615, SG-531, and SG-51 Series. Reference oscillator; clock output, supply, tolerance, and loading.
• Seiko Epson, The History of Epson Crystal Devices. Manufacturer history recording SG-51 commercialization in 1986.
• Texas Instruments, LT1054 Switched-Capacitor Voltage Converter. Basic inverter, pinout, and capacitors.
• Texas Instruments, CD74HCT123 Dual Retriggerable Monostable Multivibrator. Reset stretching and RC timing.
• Nisshinbo Micro Devices, NJM4556A Dual High-Current Operational Amplifier. Supply range, current output, and gain stability for the NJM4556A family.
• Texas Instruments, SN74HCT74, CD74HCT4040, SN74HCT08, and local FAST-logic data sheets. Adapter pinouts, thresholds, and timing.
• Motorola, M68000 User's Manual. Byte-lane selection, bus timing, and bus-error behavior.