Clock and Reset

1. Signal Summary

2. Internal Signal Reference

This table defines the clock and reset nets used by the motherboard. Signal names ending in _n are active low. Clock signals have no active-low suffix because both logic states are part of their normal waveform.

The reset nets represent different reset domains. They are not interchangeable, even when a complete motherboard reset asserts several of them at once.

This section lists nets owned by the clock and reset design. Overlay and address-decode signals such as OVERLAY_EN, OVERLAY_n, OVERLAY_WRITE_n, and ROM_ALIAS_n remain in the Bus and Decode internal signal reference. Component references, resistor references, package-pin names, and the direct SN74F74 complementary-output feedback wires are not separate motherboard signal names.

Reset-Domain Relationships

DS1233 / manual switch
        |
        v
RESET_RAW_n
        |
        v
SN74LS14 conditioner
        |
        v
RESET_n -------------------------> boot-overlay initialization
   |
   +----> LS07 ----> CPU_RESET_n ----> MC68EC000 /RESET
   |                     |
   |                     +----> LS07 ----> PERIPH_RESET_n
   |                                         |
   |                                         +--> peripheral reset adapters
   |
   +----> LS07 ----> CPU_HALT_n -----> MC68EC000 /HALT


MC68EC000 RESET instruction
        |
        +---------------------> CPU_RESET_n
                                      |
                                      +--> PERIPH_RESET_n

        does not assert RESET_n

Clock-Domain Relationships

SG-615PH
    |
    +-- MASTER_CLK_40
            |
            +-- divide by 2
                    |
                    +-- CPU_CLK_DIV2
                            |
                            +-- divide by 2
                                    |
                                    +-- CPU_CLK_10
                                            |
                                            +-- MC68EC000 CLK
                                            |
                                            +-- timeout counter CLK
                                            |
                                            +-- DRAM clock buffer
                                                    |
                                                    +-- startup/refresh counters

Signal-Use Rules

RESET_RAW_n must not be used directly as a general motherboard logic reset. Its slow transition behavior is intentional, and ordinary logic uses the conditioned RESET_n signal.

RESET_STAGE_H is local to U_RESET_COND and must not acquire additional loads or architectural meaning.

CPU_RESET_n and CPU_HALT_n connect to bidirectional, open-drain processor pins. Their pull-ups and one-way open-collector drivers are part of each net definition; neither net is an ordinary push-pull output.

Additional peripherals should use PERIPH_RESET_n rather than attaching directly to CPU_RESET_n, unless a specific peripheral interface requires direct observation of the processor pin and the resulting electrical loading has been re-verified.

CPU_CLK_DIV2 is allocated only to the second divider stage and the DRAM sequencer. Any further consumer must be documented and included in the clock-loading analysis.

Status

The names, polarity, and reset-domain boundaries in this table are frozen. Adding a consumer does not create a new signal name, but it does require the applicable clock-load or reset-load analysis to be repeated. Layout capacitance, waveform measurements, and peripheral reset fanout are post-layout verification items. The CPU clock uses the conservative timing targets defined below.

3. Master Oscillator

Y_MASTER_CLK is the installed Epson SG-615PH 40 MHz oscillator, reported as tested. It supplies MASTER_CLK_40 to the first SN74F74N stage. The PH is a 5 V CMOS-output part in a four-pin SOJ package; 40 MHz is within its 26.001 to 66.667 MHz range.

The added series datasheet omits the PH variant. The values below use Epson's SG-615PH datasheet, page 1, with the package pin map on page 2. The installed marking is recorded below. Board measurements are deferred until bring-up.

Physical Connections

Connect 100 nF + 1uF between pins 4 and 2, close to the package. This is within Epson's recommended 0.01 to 0.1 uF bypass range. Pin 1 tied to VCC meets the PH output-enable high threshold of 80 percent of VCC. Neither OE nor the divider clock is gated by reset.

Electrical Characteristics

Frequency and Pulse Width

The design accepts the installed C-grade oscillator. Its tolerance-only upper bound is 10.001 MHz at the CPU. This normal oscillator tolerance is acceptable for the MC68EC000FN10 used on the board; no oscillator or divider change is required.

At the C-grade upper frequency, the period is approximately 24.9975 ns and 40 percent is approximately 9.999 ns. That interval is measured at 50 percent of VCC. It cannot be compared directly with the F74's 4 ns high and 5 ns low requirements without accounting for the measurement thresholds and edge shape. The PH datasheet supplies no TTL-level symmetry or jitter limit. Check the loaded waveform at the divider pin before closing this item.

Startup and Reset

The oscillator runs while its supply is valid and OE is high. For power-on reset, allow its 10 ms maximum startup time from VCC reaching 4.5 V, then hold the processor's reset inputs for at least 100 ms after power and the divided clock are valid. A fixed-delay implementation therefore needs at least 110 ms from valid supply, plus allowance for divider settling and timer tolerance. A nominal 100 ms timer starting at power application does not meet this conservative sequence.

Installed-Part Record

Reported marking: sg-615PH C 40.0000 M 6270A
Model: SG-615PH
Tolerance grade: C (+/-100 ppm)
Nominal frequency: 40.0000 MHz
Additional marking: 6270A (date/lot decoding unverified)

The meaning of 6270A is not needed for the electrical design. Record measured frequency and waveform results during board bring-up.

4. CPU Clock Divider

U_CPU_CLK, a Texas Instruments SN74F74N dual positive-edge-triggered D-type flip-flop, divides MASTER_CLK_40 by four. Each half is a toggle stage with its complementary output connected to its D input.

MASTER_CLK_40 -> divide by 2 -> divide by 2 -> CPU_CLK_10

CPU_CLK_DIV2 = NOT CPU_CLK_DIV2 on each MASTER_CLK_40 rising edge
CPU_CLK_10   = NOT CPU_CLK_10 on each CPU_CLK_DIV2 rising edge

CPU_CLK_DIV2 is the 20 MHz divider node and the selected DRAM-sequencer clock. Its state allocations and memory timing belong in dram.html.

Physical Connections

A 100 nF ceramic capacitor and a 1 uF capacitor are connected in parallel between pins 14 and 7 and placed near the package.

Divider Feedback Timing and Loading

The values below are the SN74F74 limits over its recommended temperature range of 0 to 70 C at VCC = 5 V +/-0.5 V. Switching values use CL = 50 pF and RL = 500 ohms. Feedback calculations assume a steady 40 MHz input and short feedback traces. C-grade tolerance reduces the shortest steady input period to approximately 24.9975 ns; jitter and final board loading still need checking.

Logic-Level Compatibility

The following limits use VCC = 4.5 V and the SN74F74 electrical characteristics on page 2-3. The divider's D and CLK inputs also use 2.0 V and 0.8 V thresholds. Each feedback output drives one D input, and 1Q drives one CLK input; their 20 uA high-state and 0.6 mA low-state loads are within the F74's 1 mA source and 20 mA sink ratings. The second-stage complementary output also drives one SN74F04 input for the expansion clock. Its added 20 uA high or 0.6 mA low load keeps the total within the same ratings. The SG-615PH also supports the first-stage CLK input's DC load.

Startup Behavior

The divider free-runs and its asynchronous preset and clear inputs remain inactive. Its power-up phase is unspecified. The reset circuit must hold the processor in reset until MASTER_CLK_40 and CPU_CLK_10 are stable. An ordinary board reset must not stop the CPU clock.

5. Clock Distribution and Fanout

Each clock net has a defined set of consumers. Check the loading and timing effect before adding another consumer or test-point branch.

Y_MASTER_CLK
    |
    +-- MASTER_CLK_40
            |
            +-- U_CPU_CLK first-stage CLK

U_CPU_CLK first stage
    |
    +-- CPU_CLK_DIV2
            |
            +-- U_CPU_CLK second-stage CLK
            |
            +-- U_DRAM_CLK_BUF 20 MHz input

U_CPU_CLK second stage (2Q, pin 9)
    |
    R_CPU_CLK (0 ohms initially)
    |
    CPU_CLK_10
    |
    +-- MC68EC000 CLK
    |
    +-- U_TIMEOUT CD74HCT4040E CP (pin 10)
    |
    +-- U_DRAM_CLK_BUF 10 MHz input
            |
            +-- DRAM_CLK_10
                    |
                    +-- U_STARTUP_DIV CD74HCT4040E CP (pin 10)
                    +-- U_REFRESH_DIV CD74HCT4040E CP (pin 10)
                    +-- U_DRAM_CLK_BUF pin 15 -> ROM_CLK  (firmware ROM)
                    +-- U_DRAM_CLK_BUF pin 17 -> INT_CLK  (interrupt logic,
                                                           MFP divider, RTC)

The DRAM controller uses a CD74ACT244E clock buffer. Its 20 MHz output feeds four matched controller branches. Its 10 MHz output feeds the two DRAM divider counters and two further channels of the same buffer, which produce ROM_CLK and INT_CLK. Every subsystem clock derived from the 10 MHz net therefore leaves the buffer rather than the divider, so the CPU and timeout paths keep the motherboard clock to themselves. The channel assignment is in dram.html.

MASTER_CLK_40 Loading

MASTER_CLK_40 is driven directly by Y_MASTER_CLK, the SG-615PH oscillator. It presently drives only the first clock input of U_CPU_CLK.

The SG-615PH specifies operation with up to a 50 pF CMOS output load. The divider's unknown input capacitance prevents a numerical remaining budget. Include all connected loads, including the probe during testing, within that 50 pF limit.

MASTER_CLK_40 shall not be distributed around the motherboard as a convenient unrelated 40 MHz timing source. Any future consumer must be added explicitly to this load calculation.

CPU_CLK_DIV2 Loading

CPU_CLK_DIV2 drives the second divide-by-two stage and one input of U_DRAM_CLK_BUF. Buffered branches A-D drive the request synchronizer, transaction register, acknowledgement register, phase counter, state/control registers, and refresh logic as specified in dram.html.

The controller branch is one ACT input with at most 1 uA leakage and 10 pF capacitance. It fits the SN74F74's DC ratings. The divider input capacitance is not specified, so accept the branch by measuring a clean clock at both receivers. The two complementary-Q feedback paths each drive a separate D input; they are not additional loads on CPU_CLK_DIV2 or CPU_CLK_10, but their own loading affects toggle-feedback timing.

CPU_CLK_10 Loading

CPU_CLK_10 is the principal distributed clock produced by the divider. It has three consumers: the MC68EC000 CPU, the CD74HCT4040 used by the bus-timeout circuit, and one input of the DRAM CD74ACT244E clock buffer.

The divider switching characteristics used elsewhere in this document are specified with a 50 pF output test load. The known receiving-device capacitance is 40 pF maximum, leaving 10 pF between the known device loads and that test condition.

The F74's 50 pF figure is a switching-test condition, not an absolute maximum output-load rating. Those limits also specify a 500 ohm test load and defined input waveforms. A total capacitance at or below 50 pF does not by itself guarantee the published minimum and maximum delays, edge rates, or pulse widths on the board. Check the complete test conditions and loaded waveform. Exceeding 50 pF requires new timing analysis; it does not alone establish an electrical overstress condition.

CPU_CLK_10 known input load = 20 pF + 10 pF + 10 pF = 40 pF
Timing-analysis load target = 50 pF
Remaining allocation = 50 pF - 40 pF = 10 pF

C_trace + C_pads + C_socket + C_adapter + C_probe <= 10 pF

Count each capacitance once. The device input figures already describe the packaged inputs; do not add the same input-package capacitance again. A routing estimate needs the board stackup, trace geometry, and lengths. The assembled-board waveform is the acceptance result.

DC Fanout

Sources are SN74F74 page 2-3, SG-615PH page 1, M68000UM section 10.13, CD74HCT4040 section 5.5, and CD74ACT244 section 5.5. The CPU specifies input leakage at 5.25 V; the logic inputs specify leakage at their rails. These are DC checks under the cited conditions, not estimates of transient charging current. The counter uses the same 2.0 V high and 0.8 V low thresholds as the CPU, giving 0.5 V high and 0.3 V low margins from the F74's 2.5 V / 0.5 V output limits at VCC = 4.5 V.

Routing Rules

Clock traces shall be kept short and direct, with a continuous ground reference on the adjacent plane. Long stubs and unnecessary test-point branches shall be avoided.

Route CPU_CLK_DIV2 only to the second divider stage and U_DRAM_CLK_BUF. Keep the buffer root and its four controller branches local to the DRAM logic. MASTER_CLK_40 should run only from the oscillator to the divider unless another documented clock consumer is later added.

CPU_CLK_10 shall be routed from the divider to the CPU, timeout counter, and U_DRAM_CLK_BUF. The buffer's 10 MHz output supplies the startup and refresh counters. The layout must be reviewed for total capacitive load and for excessive trace length before clock timing is considered complete.

Source Termination Provision

The PCB shall provide a series-resistor footprint immediately adjacent to the CPU_CLK_10 driver output. The initial assembly value is 0 ohms so that it acts as a direct connection. Designate this provision R_CPU_CLK; the CPU, timeout, and DRAM-buffer branches are downstream of it.

No nonzero termination resistance is presently specified. If bring-up measurements show overshoot, undershoot, ringing, or multiple threshold crossings, the resistor value shall be selected from the measured waveform and actual PCB interconnect rather than guessed in advance. Any nonzero value requires another edge-rate, pulse-width, and logic-level check at both receivers. A footprint and initial value are specified here; no PCB layout or assembled termination has been verified.

Clock-Net Ownership

Status

The consumer list and 0 ohm series-link provision are defined. DC fanout checks pass under the cited datasheet conditions. The remaining checks are the F74 input-capacitance estimate, board and probe loading, and waveforms at both receivers. No separate buffer is selected; the need for one remains subject to those checks.

6. CPU Clock Timing Verification

CPU_CLK_10 is generated by dividing MASTER_CLK_40 by four with the SN74F74N divider. A nominal 40 MHz input gives a nominal 10 MHz CPU clock with a 100 ns period. The MC68EC000-specific bus-timing tables in M68000UM section 10.14 include 10 MHz operation, and the addendum's ordering table lists the FN package in the 10 MHz speed grade.

The MC68EC000FN10 supports 10 MHz operation. This design permits the installed oscillator's C-grade tolerance of +/-100 ppm, which gives a tolerance-only upper bound of 10.001 MHz after division. See the oscillator section for the frequency bounds.

Divider Input Timing

At VCC = 5 V +/-0.5 V, CL = 50 pF, and RL = 500 ohms, the SN74F74 switching table gives a minimum guaranteed maximum operating frequency of 100 MHz over 0 to 70 C. This exceeds the required 40 MHz input frequency by 60 MHz. The oscillator must also meet the divider's 4 ns minimum high and 5 ns minimum low pulse durations and its TTL input-drive requirements. The SG-615PH meets the DC drive requirements. Measure clock pulse widths at the divider input after layout because the two datasheets use different measurement conditions.

MC68EC000 Documentation Note

The project copy of M68000UM is the Ninth Edition. Section 10.8, page 10-8, still labels the general clock-timing table as applying to all processors except the MC68EC000. Its 20 MHz footnote nevertheless names the MC68EC000. This conflict does not establish the table's 10 MHz column as an exact MC68EC000FN10 specification. Section 10.9 covers the MC68008, not the MC68EC000.

The general 10 MHz column specifies 45 ns minimum high and low pulse widths and 10 ns maximum rise and fall times. Section 6.0 of the Motorola addendum gives the same values for the MC68SEC000, which is a different device. Because the available MC68EC000 documentation is ambiguous, this design uses 45 ns minimum high and low pulse widths and 10 ns maximum rise and fall times as conservative board-bring-up targets. They are verification targets, not attributed MC68EC000FN10 limits.

Duty Cycle and Edge Rates

Ideally, the 100 ns CPU clock period has 50 ns high and low intervals. Unequal low-to-high and high-to-low clock-to-Q delays in the second flip-flop change those intervals. SN74F74 page 2-4 specifies CLK-to-Q or CLK-to-complementary-Q delays of 3 to 7.8 ns for a rising output and 3.6 to 9.2 ns for a falling output over 0 to 70 C, at 4.5 to 5.5 V, CL = 50 pF, and RL = 500 ohms.

Maximum master frequency, tolerance only = 40 MHz * 1.0001 = 40.004 MHz
Shortest steady master period = 25 ns / 1.0001
Second-stage rising-edge interval = 50 ns / 1.0001, approximately 49.995 ns
Conditional minimum high width = 49.995 ns + 3.6 ns - 7.8 ns = 45.795 ns
Conditional minimum low width  = 49.995 ns + 3 ns - 9.2 ns = 43.795 ns

These estimates assume successive rising edges at the second-stage clock input remain approximately 49.995 ns apart. They account for second-stage delay asymmetry only, with constant first-stage delay and no oscillator aging or jitter. Neither is a guaranteed minimum pulse width at the CPU pin. Final verification must include first-stage edge-spacing variation, oscillator timing, actual loading, and the CPU's specified pulse-width measurement levels. The conditional low-width estimate is below the comparison value of 45 ns. The available limits therefore do not establish compliance with that value; this does not prove the circuit will fail.

The F74 switching table gives propagation delays, not guaranteed output rise and fall times. Its note 3 refers to load circuits and waveforms in Section 1 of the source databook, which is not included in this standalone PDF. Those measurement definitions are still needed. Output edge rates remain unverified at the CPU pin with the CPU, timeout counter, refresh counter, and board capacitance attached.

Status and Sources

The SN74F74N implementation and divide-by-four ratio are frozen. Exact CPU pulse-width, edge-rate, and load checks are deferred until the routed board can be measured. The C-grade oscillator tolerance is accepted.

Sources are the SN74F74 datasheet, SDFS046A, pages 2-1 through 2-4, downloaded from Texas Instruments; M68000UM, Ninth Edition, sections 10.8 and 10.14; and the M68000 manual addendum, section 6.0 and the ordering information on page 25.

7. Power-On Reset

U_RESET_SUP is a Dallas Semiconductor DS1233-5 EconoReset supervisor. It monitors the motherboard +5 V rail and generates the active-low raw reset signal RESET_RAW_n.

The datasheet lists the lead-free TO-92 ordering form as DS1233-5+. The + suffix denotes the package lead finish and does not change the reset function.

+5 V ---- U_RESET_SUP pin 3 (VCC)
GND ----- U_RESET_SUP pin 1 (GND)

U_RESET_SUP pin 2 (RST) ---- RESET_RAW_n
                              +-- manual switch and 1 nF capacitor to GND
                              +-- LS14 stage 1 -- LS14 stage 2 -- RESET_n
                                                                +-- overlay preset
                                                                +-- LS07 CPU drivers

Selection Rationale

The DS1233-5 combines supply-voltage monitoring, reset-delay timing, and manual-reset switch monitoring in a three-pin through-hole device. It does not depend on an external RC network to establish the required power-on reset interval.

Supply Monitoring

These limits are from page 5 of the DS1233 datasheet. The AC table requires at least 300 us for VCC to fall from 4.75 V to 4.00 V. A faster collapse is outside that specified condition, so the 100 ns assertion delay must not be treated as an unconditional brownout guarantee.

The MC68EC000 supply specification is 5 V +/-5 percent, or 4.75 to 5.25 V (M68000UM section 10.13). The DS1233-5 may not trip until 4.50 V, leaving up to 0.25 V of CPU undervoltage before reset. On a slow power ramp it can also finish its timer before the CPU supply reaches 4.75 V. The threshold values are verified; complete CPU brownout protection and safe release are not.

Power-On Timing

On power-up, the DS1233 keeps RESET_RAW_n asserted until the +5 V rail has crossed the monitored supply threshold and the internal reset timer has completed.

The minimum reset-active interval is 250 ms after the supervisor's threshold is crossed. It exceeds the CPU's 100 ms reset requirement only if power and clock become valid early enough within that interval.

The oscillator starts within 10 ms after reaching its minimum supply of 4.5 V. On a rising supply that stays valid, the supervisor's threshold is at or above this voltage, so the oscillator can use at most the first 10 ms of the supervisor's minimum delay.

t0: supply crosses the supervisor's actual 4.50 to 4.75 V threshold
    and remains above it

Oscillator startup allowance: at most 10 ms from reaching 4.5 V
Earliest supervisor release:  t0 + 250 ms
Conditional post-startup hold: 250 ms - 10 ms = 240 ms
CPU reset requirement:        100 ms after valid power and clock

The 240 ms difference is a conditional timing budget, not proof of safe CPU release. The rail must reach and remain within 4.75 to 5.25 V, and the divided clock and isolation drivers must be valid, at least 100 ms before release at the CPU pins. In the 250 ms minimum case, this requires valid CPU conditions by t0 + 150 ms. Verify that condition against the actual supply ramp and driver circuit.

Physical Connections

The TO-92 pin numbering in the datasheet is shown from the bottom view: pin 1 is ground, pin 2 is RST, and pin 3 is VCC.

A 100 nF + 1 uF ceramic decoupling capacitor shall be placed between VCC and ground close to U_RESET_SUP.

RESET_RAW_n Electrical Behavior

The DS1233 contains an internal pull-up resistor on its RST pin. The datasheet specifies this resistor as 3.75 kohm minimum, 5 kohm typical, and 6.25 kohm maximum.

When reset is asserted, the device can sink at least 8 mA while maintaining a reset-output voltage of no more than 0.4 V.

RESET_RAW_n drives only the first SN74LS14 input, SW_RESET, and C_RESET_SW. The two-stage conditioner drives RESET_n and isolates the raw RC node from the overlay and LS07 inputs. The electrical verification section gives the separate load budgets. No external pull-up is selected.

The supervisor's operating-current limit is 50 uA. Its output capacitance is at most 10 pF. Include both the internal pull-up current and external loads in the reset sink-current budget. For example, the internal resistor alone draws approximately (5.5 V - 0.4 V) / 3.75 kohm = 1.36 mA at a 0.4 V reset level. The 8 mA output rating does not define how much current the released node can source; that depends on its pull-up.

Manual Reset Capability

The DS1233 also monitors its RST node for an external switch closure. Manual Reset defines SW_RESET and the selected 1 nF C_RESET_SW, including the separate debounce and reset-active intervals.

Reset Release and HCT Inputs

The SN74HCT74 preset requires input rise/fall times no greater than 500 ns. RESET_RAW_n feeds two SN74LS14 Schmitt stages, and the conditioned RESET_n output drives the preset, so the reset-node capacitor does not set the preset's RC release time.

The SN74LS14 accepts slow input ramps. Its datasheet does not give a guaranteed output rise/fall time, so the conditioned preset waveform still requires verification. Component and layout evidence gaps are listed in electrical verification.

Isolation from Processor /RESET

RESET_n is a motherboard reset-request signal and remains separate from the MC68EC000's bidirectional /RESET pin.

The processor /RESET pin must not be connected directly to the DS1233 RST node. The MC68EC000 can assert its own /RESET pin while executing the RESET instruction. If this assertion were allowed to pull RESET_RAW_n low, the DS1233 could interpret the processor-generated assertion as an external reset request and extend it into a full motherboard reset.

Instead, RESET_n will drive the processor /RESET and /HALT inputs through separate LS07 channels defined in the processor-reset section. They must preserve one-way reset propagation:

RESET_n -----------> CPU /RESET driver -----------> CPU /RESET
    |
    +---------------> CPU /HALT driver ------------> CPU /HALT

CPU /RESET ---------X---------> RESET_n

X = no feedback path

Consequently, power-on reset and manual motherboard reset reinitialize board state such as the boot overlay, while a processor-generated RESET instruction does not re-enable the boot overlay.

Status

The DS1233-5 is frozen as the motherboard power-on and supply-monitoring reset supervisor. Its RST node is RESET_RAW_n. Power-on reset duration and supply threshold are recorded from the datasheet; full board-level verification remains open.

Supply-ramp and brownout coverage, reset-node loading, conditioned edges, and CPU /RESET and /HALT timing are post-layout checks. The supervisor selection is final.

Source

Dallas Semiconductor / Analog Devices, DS1233 5V EconoReset, revision 2 (August 2025), pages 1, 2, 5, and 6; M68000UM, sections 5.5 and 10.13; and SN74HCT74, recommended operating conditions.

8. Manual Reset

Manual motherboard reset is requested by SW_RESET, a normally-open momentary pushbutton connected between RESET_RAW_n and ground.

The DS1233 directly monitors its RST output node for an externally applied low level. Therefore no separate switch-debounce logic or reset one-shot is required.

                  DS1233-5
                     |
                     +---- RESET_RAW_n ----+---- two LS14 stages -> RESET_n
                                      |
                                      +---- SW_RESET ---- GND
                                      |
                                      +---- C_RESET_SW -- GND

Switch Function

SW_RESET is a single-pole, single-throw, normally-open momentary switch.

Debounce and Reset Extension

Mechanical switch bounce is handled by the DS1233. When a low-going edge is detected on RESET_RAW_n, the supervisor takes control of the reset node and keeps it asserted.

After the debounce timer expires, the DS1233 checks for switch release. If the button is still held, reset stays asserted. Once release is detected, a separate reset-active interval follows. A short press can therefore leave part of the debounce interval as well as the reset interval after physical switch release.

Both timing ranges are specified over -40 to 85 C at VCC = 4.5 to 5.5 V. The 250 ms minimum reset-active interval exceeds the CPU reset durations listed below, provided power and clock remain valid and the isolation stages deliver the required low levels to both CPU reset pins. This does not close the supply and release-edge checks in the power-on section.

Reset-Node Capacitor

C_RESET_SW is connected directly between RESET_RAW_n and ground as required by the DS1233 pushbutton interface.

The DS1233 permits a capacitance from 100 pF through 0.01 uF for pushbutton operation. The selected 1 nF value is inside this range and also exceeds the 500 pF minimum for applications using an external pull-up to obtain additional reset-node current. That configuration also requires an external pull-up of at least 1 kohm; the capacitor alone does not increase drive current. No external pull-up is selected.

C_RESET_SW does not establish the motherboard reset duration. The DS1233 internal timer sets that duration. This is the same reset-node capacitor described in the power-on section, not an additional capacitor. Implementation may choose any suitable 1 nF ceramic part whose tolerance keeps it within the DS1233 range of 100 pF to 10 nF.

The selected 1 nF capacitor remains on RESET_RAW_n. Two SN74LS14 Schmitt stages isolate its slow RC release from the overlay preset. The electrical checks record raw-node loading and the remaining conditioned-output edge check.

Reset Switch Wiring

The reset switch requires only two electrical connections:

SW_RESET terminal 1 -> RESET_RAW_n
SW_RESET terminal 2 -> GND

No separate debounce timer is selected. Place C_RESET_SW near the supervisor, between its RST node and ground. The required capacitor still forms an RC release edge with the pull-up; reset-edge conditioning is separate from switch debouncing.

If the switch is mounted remotely from the motherboard, its wiring should be kept reasonably short and routed with a nearby ground return so that the reset input does not become an unnecessary noise pickup path. Check exposed front-panel wiring for noise and ESD susceptibility during the enclosure design.

Interaction with Other Reset Sources

Manual reset and power-on reset share the same board-level RESET_RAW_n domain. Both therefore perform the same motherboard initialization, including re-enabling the boot ROM overlay.

This remains distinct from a processor-generated RESET instruction. The CPU's bidirectional /RESET pin does not feed back into RESET_RAW_n, so software execution of RESET does not simulate pressing SW_RESET and does not re-enable the boot overlay.

Physical Switch Selection

The electrical switch requirement is frozen as a normally-open momentary SPST contact. The specified switch is the C&K FP11SPC1B1TP00, the same part used for the front-panel power button in power-control.html and the NMI button in interrupts.html. A different actuator style may be substituted if the enclosure and front-panel design require it, provided the contact remains normally-open momentary SPST.

Status

Manual-reset electrical behavior is frozen: SW_RESET pulls RESET_RAW_n to ground, the DS1233 performs switch debouncing and reset extension, and C_RESET_SW is 1 nF.

The exact mechanical pushbutton remains an enclosure-level decision. The isolated drivers from conditioned RESET_n to the MC68EC000 /RESET and /HALT pins use the SN74LS07N defined below. Loaded transition times are post-layout checks.

Source

Dallas Semiconductor / Analog Devices, DS1233 5V EconoReset, revision 2, page 2 (pushbutton operation) and page 5 (AC limits); SN74HCT74, recommended operating conditions.

9. Processor /RESET and /HALT Handling

The MC68EC000 /RESET and /HALT pins are bidirectional active-low signals. Both pins are open-drain when driven by the processor.

An external processor reset requires both signals to be asserted at the same time. However, the two CPU pins must remain electrically separate because the processor can also assert either signal independently: execution of the RESET instruction asserts /RESET, while processor halt conditions can cause the processor to assert /HALT.

Board-level RESET_n therefore drives the two processor pins through separate open-collector buffer stages.

The processor MODE pin must be high or unconnected during reset so the MC68EC000 starts in 16-bit bus mode.

                         +5 V
                          |
                       3.9 kohm
                          |
RESET_n ---> LS07 ------+------ CPU_RESET_n ---> MC68EC000 /RESET
             open       |
           collector    +------ CPU may also pull this node low


                         +5 V
                          |
                       3.9 kohm
                          |
RESET_n ---> LS07 ------+------ CPU_HALT_n ----> MC68EC000 /HALT
             open       |
           collector    +------ CPU may also pull this node low

Driver Selection

U_RESET_DRV is a Texas Instruments SN74LS07N, a six-channel non-inverting buffer with open-collector outputs in a 14-pin PDIP package.

A non-inverting open-collector buffer is required because RESET_n already has the desired active-low polarity. A low input causes the corresponding LS07 output transistor to pull the processor signal low. A high input releases the processor signal instead of actively driving it high.

Physical Connections

A 100 nF + 1uF ceramic decoupling capacitor shall be placed directly between pins 14 and 7.

Channel 3 (pins 5 and 6) is assigned to peripheral reset in Reset Distribution. Tie unused inputs 4A, 5A, and 6A (pins 9, 11, and 13) to ground and leave outputs 4Y, 5Y, and 6Y (pins 8, 10, and 12) unconnected. Recheck loading if these channels are assigned later.

Processor-Side Pull-Ups

Because both the LS07 outputs and the MC68EC000 outputs are open-collector/open-drain, each processor control line requires its own pull-up resistor.

Pull-Up Current Verification

The MC68EC000-specific DC characteristics guarantee VOL <= 0.5 V for the processor /HALT output while sinking 1.6 mA. The /RESET output has the stronger guarantee of 5.0 mA at the same maximum low voltage.

/HALT therefore sets the worst-case pull-up-current requirement.

R nominal = 3.9 kohm
R minimum at -5% = 3.705 kohm

VCC maximum = 5.25 V
CPU VOL maximum = 0.5 V

Pull-up load at the CPU's specified maximum low voltage
    = (5.25 V - 0.5 V) / 3.705 kohm
    = 1.28 mA

Resistor-current upper bound, taking the low node as 0 V
    = 5.25 V / 3.705 kohm
    = 1.42 mA

Both values are below the 1.6 mA HALT sink rating

Each pull-up is within the processor's sink rating while its LS07 output is released. This checks the defined resistor load; additional peripheral inputs or pull-ups require another current calculation.

The SN74LS07 guarantees at most 0.4 V while sinking 16 mA, within its 4.75 to 5.25 V supply and 0 to 70 C operating ranges. This meets the CPU's 0.8 V low-input limit for the defined pull-ups. Operation below 4.75 V is not guaranteed, so this stage does not close the DS1233 brownout-coverage gap.

Supervisor Loading and Released Levels

The LS07 off-state limit is specified at a 30 V output; using its 250 uA value at the board's 5 V level is a conservative screening assumption, not a separate 5 V specification. The CPU leakage value comes from M68000UM section 10.13. Final loading must include all receivers and protection components. The released LS07 output cannot source a high level; each pull-up must overcome the node's leakage.

One-Way Motherboard Reset Propagation

The open-collector buffers provide intentional one-way isolation between the motherboard reset domain and the bidirectional processor pins.

RESET_n
   |
   +--------> LS07 --------> CPU_RESET_n
   |                           ^
   |                           |
   |                     CPU RESET instruction
   |
   +--------> LS07 --------> CPU_HALT_n
                               ^
                               |
                         CPU halt condition


CPU_RESET_n ----X----> RESET_n
CPU_HALT_n  ----X----> RESET_n

Consequently, power-on or manual motherboard reset asserts both CPU control pins and also resets motherboard state such as the boot overlay. A processor-generated RESET instruction asserts only CPU_RESET_n and does not reassert RESET_n.

Peripherals that are intended to respond to the processor RESET instruction use the buffered PERIPH_RESET_n domain defined below. Do not add direct CPU_RESET_n loads without review. Peripherals that must respond only to complete motherboard reset shall instead use the RESET_n domain. Exact peripheral reset connections belong in the corresponding subsystem documents.

HALT Behavior

During an external motherboard reset, the second LS07 channel pulls CPU_HALT_n low from the same request that asserts CPU_RESET_n. The channels have separate delays; verify that both CPU pins stay low together for the required reset interval. Exact simultaneous edges are not guaranteed.

Outside motherboard reset, the LS07 output is released. The processor can therefore assert CPU_HALT_n itself to report an internally detected halt condition without driving against the reset circuit.

CPU_HALT_n is not fed back into RESET_n. A processor halt condition therefore does not automatically become a motherboard reset request.

Transition-Time Verification

M68000UM section 10.14, page 10-25, parameter 32 specifies 150 ns maximum HALT and RESET input transition time for the MC68EC000, including the 10 MHz grade. Check both assertion and release at the CPU pins. Release depends on each pull-up, total capacitance, and off-state leakage.

The CPU's published input capacitance is 20 pF maximum under its section 10.13 test conditions. With the maximum 4.095 kohm pull-up, that input alone gives an 81.9 ns RC time constant. A time constant is not the complete input transition time; include LS07 output capacitance, routing, sockets, probes, and any peripherals, and use the manual's measurement levels. The LS07 datasheet supplies no guaranteed output-capacitance value, so accept the final node from its measured release time and thresholds rather than an assumed capacitance.

LS07 section 6.6 specifies propagation delays at 5 V and 25 C with a 110 ohm load and 15 pF capacitance. Those conditions do not match the selected 3.9 kohm pull-ups, and propagation delay is not an output rise-time specification. Verify the loaded waveforms against 150 ns before marking this interface complete. The LS07 is not a Schmitt trigger, so the edge conditioning is done upstream by the two-stage SN74LS14. Its loaded output edge remains a separate verification item.

Status

Processor reset and halt isolation is frozen: U_RESET_DRV is an SN74LS07N, two separate non-inverting open-collector channels are driven by RESET_n, and the processor-side CPU_RESET_n and CPU_HALT_n nets each use a 3.9 kohm pull-up to +5 V.

The selected parts and connections are fixed. Measure the 150 ns transitions, total loading, conditioned output edges, and supply-ramp behavior after layout.

Sources

Motorola, M68000 User's Manual, sections 3.6, 3.11, 5.5, 10.13, and 10.14; Texas Instruments, SN74LS07, revision D, sections 5, 6.3, 6.5, and 6.6; and DS1233, page 5.

10. Reset Distribution

The motherboard distinguishes between a complete board reset and the processor's bidirectional /RESET signal.

RESET_n represents a power-on or manual motherboard reset. It initializes board-specific state such as the boot-ROM overlay and externally asserts both processor /RESET and /HALT.

CPU_RESET_n is the actual MC68EC000 /RESET pin. It is asserted during a motherboard reset, but the processor can also assert it while executing the RESET instruction. In that case external devices are reset without reinitializing the processor itself.

Peripheral reset distribution must therefore originate from CPU_RESET_n rather than directly from RESET_n when the peripheral is intended to honor the processor RESET instruction.

DS1233 supply supervision / manual switch
                  |
                  v
             RESET_RAW_n
                  |
            two LS14 stages
                  |
               RESET_n
                  +--> boot overlay (conditioned reset)
                  +--> LS07 channel 1 --> CPU_RESET_n
                  +--> LS07 channel 2 --> CPU_HALT_n

CPU RESET instruction -----------------> CPU_RESET_n
                                              |
                                              v
                                         LS07 channel 3
                                              |
                                              v
                                        PERIPH_RESET_n
                                              |
                                              v
                                   peripheral reset interfaces

CPU_RESET_n and PERIPH_RESET_n must not feed back into RESET_n.

Peripheral Reset Buffer

Channel 3 of U_RESET_DRV, the existing SN74LS07N, buffers CPU_RESET_n into the active-low peripheral-reset distribution signal PERIPH_RESET_n.

The SN74LS07 is non-inverting, so the signal polarity is preserved:

Physical Connection

PERIPH_RESET_n requires a pull-up to +5 V because the SN74LS07 output is open collector.

R_PERIPH_RESET is 1 kohm, +/-5 percent, rated at least 0.125 W, from +5 V to PERIPH_RESET_n. The value is final. Verify the total receiver leakage, capacitance, and delivered pulse width after the peripheral interfaces and board layout are complete.

Receiver leakage lowers the released level further. For a receiver requiring VIH, check VCC(min) - R(max) * I_leak(total) >= VIH. For a simple unloaded RC model, the 10-to-90-percent rise time is approximately 2.2 * R * C; leakage and distributed wiring require a more complete model. No capacitance or edge-time allowance is assigned until the receivers' thresholds and transition limits are known.

The defined MC68901 reset input adds at most 10 uA leakage and 10 pF capacitance to PERIPH_RESET_n. Its leakage drops the released level by at most 10.5 mV through the 1.05 kohm maximum pull-up, and its 2.0 V TTL high threshold matches the reset driver.

The two expansion-slot control buffers add two SN74HCT244 inputs, totaling at most 2 uA leakage and 20 pF capacitance. Their leakage lowers the released level by at most 2.1 mV through the 1.05 kohm maximum pull-up. Each buffer then drives one connector reset branch; card loads do not appear directly on PERIPH_RESET_n. See Expansion Slots.

The OPL3 reset adapter adds one CD74HCT123 input and one SN74HCT08 input, totaling at most 2 uA leakage and about 20 pF nominal input capacitance. Their leakage lowers the released level by at most 2.1 mV through the 1.05 kohm maximum pull-up. The adapter stretches every peripheral reset locally, so the YMF262 does not load PERIPH_RESET_n directly.

CPU_RESET_n Buffer Loading

The additional LS07 input is a small load on the bidirectional processor-reset node. The LS07 uses TTL-compatible input thresholds: a LOW input is guaranteed at or below 0.8 V and a HIGH input is guaranteed at or above 2.0 V.

Its maximum LOW-state input current is 0.2 mA. With the 3.9 kohm CPU_RESET_n pull-up, the worst-case current that the MC68EC000 must sink while asserting its own /RESET output is:

R_CPU_RESET minimum = 3.9 kohm * 0.95 = 3.705 kohm
Pull-up load at VOL = 0.5 V = (5.25 V - 0.5 V) / 3.705 kohm = 1.28 mA
Pull-up current upper bound at 0 V = 5.25 V / 3.705 kohm = 1.42 mA
Additional LS07 low-state input current = 0.20 mA

Conservative CPU /RESET sink-load budget = 1.42 mA + 0.20 mA = 1.62 mA
MC68EC000 /RESET sink rating = 5.0 mA at VOL <= 0.5 V

Therefore sensing CPU_RESET_n with one LS07 input does not overload the processor's /RESET output under this current budget. The added input is on CPU_RESET_n only; the weaker CPU_HALT_n output does not carry it.

The high-state input load is another 20 uA. Including the existing 250 uA LS07 output-leakage screening allowance and 20 uA CPU input leakage gives 290 uA on CPU_RESET_n. Its released-level estimate is 4.75 V - 4.095 kohm * 290 uA = 3.56 V, above the 2.0 V threshold. The 250 uA output limit is specified at 30 V, so using it here remains a screening assumption. Added input capacitance must also be included in the CPU's 150 ns reset-transition check; LS07 input capacitance is not specified.

Reset Domains

Peripheral Interface Boundary

PERIPH_RESET_n is a motherboard reset-distribution source, not necessarily the final reset pin connection for every peripheral.

Every reset-capable peripheral shall derive its reset from PERIPH_RESET_n. Each peripheral document must verify its reset polarity, input thresholds, minimum reset duration, release timing, and any required synchronization. An active-high reset needs inversion. A device without a reset pin needs its own initialization method. The RESET instruction drives the CPU node for 124 clocks, nominally 12.4 us at 10 MHz; it does not invoke the DS1233's 250 ms minimum timer. Check the delivered pulse after buffer and adapter delays. LS07 switching values measured with 110 ohms and 15 pF do not apply directly to this 1 kohm distribution net.

Peripheral pages must not connect additional loads directly to CPU_RESET_n without updating the CPU reset-node loading analysis. The buffered PERIPH_RESET_n domain exists to avoid uncontrolled fanout on the bidirectional processor pin.

Board-Only Reset State

State that must be restored only by power-on or manual motherboard reset uses RESET_n, not PERIPH_RESET_n.

In particular, the boot-overlay state belongs to the RESET_n domain. A processor RESET instruction must reset external devices without re-enabling the low-address firmware alias.

Status

The reset-domain architecture and peripheral-reset buffer topology are frozen. Channel 3 of U_RESET_DRV generates PERIPH_RESET_n from CPU_RESET_n.

R_PERIPH_RESET is frozen at 1 kohm with the resistor-current budget shown above. The MFP, MIDI, OPL3, RTC, floppy, and VGA shall use this domain wherever the selected device provides or needs a reset input. Their pages must define the final pin connection and any polarity adapter. Fanout, leakage, capacitance, release edges, and delivered pulse widths are post-layout checks.

The MC6850 has no reset pin. The MIDI design instead requires a control-register master reset after power-up and after every processor RESET sequence.

Source

Motorola, M68000 User's Manual, sections 3.6, 5.5, 10.13, and 10.14; and Texas Instruments, SN74LS07, sections 5, 6.3, 6.5, and 6.6.

11. Boot-Overlay Reset Connection

The boot-ROM overlay is motherboard state and is initialized by RESET_n, not by the processor's bidirectional CPU_RESET_n signal.

The conditioned RESET_n output connects to U_OVERLAY pin 4, the active-low asynchronous preset. The raw DS1233 output is isolated by two SN74LS14 Schmitt stages.

RESET_n
   |
   +----------------------> U_OVERLAY 1/PRE
                                  |
                                  +-- Q  = OVERLAY_EN
                                  |
                                  +-- /Q = OVERLAY_n

Reset-State Behavior

The SN74HCT74 asynchronous preset input is active low. When 1/PRE is low while 1/CLR is inactive, the flip-flop forces Q high and /Q low independently of the D and clock inputs.

Therefore assertion of motherboard reset produces:

RESET_n = 0

U_OVERLAY 1/PRE = 0

OVERLAY_EN = 1
OVERLAY_n  = 0

OVERLAY_EN = 1 is the required boot state. The firmware EEPROM alias is enabled for the low 128 KiB address range. This is the reset mapping, not an active CPU bus cycle during reset.

Relationship to ROM Alias Logic

The bus decoder defines the raw boot-alias condition as:

ROM_ALIAS_ADDR_n = LOW128_n OR OVERLAY_n

While reset is asserted:

OVERLAY_n = 0

At an address inside $000000-$01FFFF:

LOW128_n = 0

ROM_ALIAS_ADDR_n
    = 0 OR 0
    = 0

The raw alias address condition is true.
Actual bus-cycle qualification is separate:
ROM_ALIAS_n = ROM_ALIAS_ADDR_n OR NORMAL_MISC_n

With valid reset release and normal-cycle qualification, the initial stack-pointer and program-counter fetches from addresses beginning at $000000 are directed to firmware rather than DRAM.

Reset Release

When RESET_n returns high, the asynchronous preset becomes inactive. This releases control of the flip-flop but does not by itself request that the overlay be disabled.

OVERLAY_EN therefore remains high after motherboard reset is released. Firmware later disables the low-address alias using the SYSREG0 overlay-write mechanism defined in bus-and-decode.html.

The exact D-input and clocking implementation of U_OVERLAY is owned by bus-and-decode.html and is not redefined here.

Processor RESET Instruction

CPU_RESET_n is deliberately not connected to the asynchronous preset input of U_OVERLAY.

When the MC68EC000 executes a RESET instruction, it can assert CPU_RESET_n and consequently PERIPH_RESET_n, but the board-level RESET_n signal remains inactive.

CPU executes RESET instruction:

CPU_RESET_n    = 0
PERIPH_RESET_n = 0

RESET_n        = 1

U_OVERLAY 1/PRE remains inactive
OVERLAY_EN remains unchanged

Thus a processor RESET instruction resets external devices without restoring the boot-ROM alias, unless an independent board reset occurs. Any RESET_n assertion, including a supervisor brownout reset, reinitializes the overlay when the flip-flop supply is valid.

Reset-Domain Summary

Electrical Verification

The HCT74 preset requires VIH at least 2 V, VIL no greater than 0.8 V, a low pulse of at least 20 ns at 4.5 V, and input rise/fall times no greater than 500 ns. Input leakage is at most 1 uA in magnitude and input capacitance is at most 10 pF.

RESET_n is driven by the second SN74LS14 stage, with two LS07 inputs and this preset as its loads. A direct DS1233-to-preset RC calculation does not describe this net. See electrical verification for the raw-node and conditioned-node tables, current margins, and the unspecified LS14 output-edge limit.

Preset and Clear Overlap

The bus document grounds D and CLK and uses OVERLAY_WRITE_n on asynchronous clear to disable the overlay. Releasing preset retains the boot state only if clear is inactive. Both asynchronous inputs low force both Q and /Q high, so the outputs are no longer complementary.

A motherboard reset arriving during a SYSREG0 write can overlap preset and clear before the processor and decoder respond. Holding the CPU in reset eventually stops writes, but does not prove that the inputs never overlap. Verify that clear returns high while preset is still held low, and that the boot state is restored before CPU reset release. The overlay-disable circuit remains defined in the bus document.

Status

The boot-overlay reset-domain assignment is frozen. Check the conditioned output edge and preset/clear overlap after layout. With clear inactive, RESET_n asserts the active-low preset input of U_OVERLAY, forcing OVERLAY_EN high and OVERLAY_n low.

CPU_RESET_n and PERIPH_RESET_n do not initialize the overlay. The existing overlay-disable implementation remains defined exclusively in bus-and-decode.html.

Source

Texas Instruments, SN54HCT74 / SN74HCT74 Dual D-Type Positive-Edge-Triggered Flip-Flops With Clear and Preset , datasheet, sections 5.2, 5.4, 5.5, and 7.3; SN74LS07, section 6.5; DS1233, page 5; and Bus and Decode, overlay implementation.

12. Reset Release Sequencing

The +5 V supply, master oscillator, CPU clock divider, and boot-overlay state must be valid before the MC68EC000 begins its reset-vector bus cycles. The sequence below defines the required operation. Supply-ramp, reset-edge, and overlay preset/clear checks are deferred until board bring-up.

The clock source and divider are free-running and are not controlled by reset. The DS1233 therefore delays processor release rather than attempting to start the clock simultaneously with the processor.

This sequence assumes valid device supplies, inactive overlay clear, and compliant reset waveforms. Reset outputs are not guaranteed from zero volts, and the LS14 conditioner and LS07 drivers require at least 4.75 V.

+5 V power applied
       |
       +-- DS1233 detects supply
       |       |
       |       +-- RESET_RAW_n asserted -> two LS14 stages -> RESET_n
       |               |
       |               +-- boot overlay forced enabled
       |               +-- CPU_RESET_n asserted through LS07
       |               +-- CPU_HALT_n asserted through LS07
       |
       +-- SG-615PH starts
       |       |
       |       +-- MASTER_CLK_40 becomes valid
       |               |
       |               +-- divider begins free-running
       |                       |
       |                       +-- CPU_CLK_10 becomes valid
       |
       +-- supply crosses actual DS1233 threshold and stays above it
               |
               +-- DS1233 reset timer starts
               |
               +-- at least 250 ms
               |
               +-- RESET_RAW_n released -> two LS14 stages -> RESET_n
                       |
                       +-- overlay preset released;
                       |   OVERLAY_EN remains set
                       |
                       +-- CPU_RESET_n released
                       +-- CPU_HALT_n released
                               |
                               +-- MC68EC000 begins reset sequence
                                       |
                                       +-- fetch initial SSP from $000000
                                       +-- fetch initial PC from $000004
                                       |
                                       +-- vector reads use ROM alias

Power-Up Sequence

Power-Up Reset Margin

The MC68EC000-specific AC electrical specifications state that the processor must remain in the reset state for 520 clocks during power-up to allow its internal circuitry to stabilize.

CPU clock = 10 MHz
CPU clock period = 100 ns

520 clocks * 100 ns
    = 52 us

The general reset-operation section of the M68000 User's Manual gives the more conservative requirement that initial external reset be held for at least 100 ms.

The board retains the conservative 100 ms hold after power and clock become valid. The DS1233's 250 ms minimum delay can cover both requirements, but its timer starts at its own threshold. A slow ramp can start that timer before the CPU reaches its 4.75 V minimum supply.

MC68EC000 stabilization: 520 valid clocks = 52 us at nominal 10 MHz
At 9.999 MHz: 520 / 9.999 MHz = approximately 52.0052 us
Board initial-reset hold after valid power and clock: 100 ms
DS1233 minimum delay from its threshold crossing:    250 ms

The durations have different starting conditions.

Oscillator Startup Margin

The SG-615PH specifies 10 ms maximum startup after reaching its 4.5 V minimum supply. On a rising rail that stays valid, the DS1233-5 threshold is at or above that voltage. The following budget assumes that ramp behavior; divider timing and CPU supply validity must also be checked.

t0 = actual DS1233 threshold crossing, with supply remaining above it

Earliest supervisor release:       t0 + 250 ms
Latest oscillator startup:         t0 +  10 ms
Conditional post-startup interval:       240 ms

For the board's 100 ms initial-reset hold:
valid CPU power, clock, and reset levels are required by t0 + 150 ms.

Verify the actual supply ramp and the common low interval at both CPU pins. The CPU and LS07 require 4.75 to 5.25 V. A rail that stalls below 4.75 V can let the supervisor timer expire without meeting that condition. The power-on reset section records this threshold gap. The CPU clock checks remain separate from the reset-duration budget.

Boot-Overlay State at Release

With valid supply and asynchronous clear inactive, a low RESET_n presets U_OVERLAY:

OVERLAY_EN = 1
OVERLAY_n  = 0

When RESET_n rises, the preset input becomes inactive, but this does not clear the flip-flop. Therefore OVERLAY_EN remains high after reset release.

No software action is needed to establish the alias. Hardware must restore the preset state before CPU release, including when reset interrupts a SYSREG0 overlay-disable write. Verify preset/clear overlap and preset release as described in the boot-overlay reset section.

With those conditions met, each 32-bit vector is read as two 16-bit transfers in the selected 16-bit bus mode:

$000000 and $000002: initial SSP -> boot ROM alias
$000004 and $000006: initial PC  -> boot ROM alias

Processor /RESET and /HALT Release

Both processor control pins are driven from the same RESET_n source through separate channels of U_RESET_DRV. There is therefore no intentional sequencing delay between processor /RESET and /HALT.

When RESET_n rises, each SN74LS07 open-collector output releases its corresponding processor node. The 3.9 kohm pull-up on each node then raises that signal toward +5 V.

LS07 channel behavior, pull-up tolerance, and node capacitance can produce different threshold-crossing times. Check the common asserted interval and both release waveforms at the CPU pins; a shared source does not prove simultaneous release or a specified skew bound.

Processor Input Transition Requirement

MC68EC000 AC specification 32 gives a maximum input transition time of 150 ns for both /HALT and /RESET. Use the manual's measurement conventions when checking the waveforms.

The final release-edge calculation therefore must prove:

CPU_RESET_n transition time <= 150 ns
CPU_HALT_n  transition time <= 150 ns

Each 3.9 kohm +/-5 percent pull-up can reach 4.095 kohm. The CPU's 20 pF maximum input capacitance alone gives an 81.9 ns RC time constant. That is a partial-load calculation, not a 150 ns transition-time pass. Include LS07 output capacitance, routing, sockets, probes, leakage, and the channel-3 input on CPU_RESET_n. The LS07 datasheet does not specify those pin capacitances, so final transition times require additional load data and measurements on the assembled board. See processor reset and halt handling for the driver limits. Check assertion edges as well as release.

RESET_n Release Edge

C_RESET_SW remains 1 nF on RESET_RAW_n. The raw node now feeds two SN74LS14 Schmitt stages, which drive RESET_n. Verify the conditioned output against the HCT74's 500 ns input-transition limit; LS14 propagation delay is not an output rise-time guarantee. The electrical checks separate missing component limits from deferred PCB parasitics.

Peripheral Reset Release

PERIPH_RESET_n is generated from CPU_RESET_n through another open-collector LS07 channel. Channel 3 starts releasing its output as CPU_RESET_n is recognized high at its input. This does not specify the threshold-crossing order at the CPU and peripheral pins or guarantee a recovery delay.

Exact peripheral readiness after reset is not assumed by this document. Each peripheral page must verify its device-specific reset recovery time before firmware accesses that device.

The initial vector reads select the firmware EEPROM alias. Peripheral recovery need not delay them provided resetting devices neither drive nor hold shared bus signals. Verify that condition and each device's recovery time in the peripheral pages before firmware accesses it. See reset distribution for the peripheral pull-up and post-layout load budget.

Status

The free-running clock, shared board-reset source, and overlay reset domain are unchanged. Datasheet durations support the intended sequence under the conditions above; board-level release timing is not yet verified.

Remaining checks are the supply ramp, valid divided clock, common CPU reset hold, loaded reset edges, overlay preset/clear overlap, and peripheral recovery. No additional datasheet is needed to establish the durations cited here. Completing the edge checks needs board loading and waveform measurements; the LS07 datasheet omits pin capacitances.

Sources

Motorola, M68000 8-/16-/32-Bit Microprocessors User's Manual, manual, section 5.5 and section 10.14, parameter 32 and note 4; Analog Devices, DS1233, pages 2, 3, and 5 (also stored locally); Texas Instruments, SN74HCT74, sections 5.2 and 7.3, and SN74LS07, sections 6.3, 6.5, and 6.6; Epson, SG-615PH, specifications.

13. Electrical and Timing Verification

Reset timing is divided into two electrical domains. RESET_RAW_n is the relatively slow supervisor and pushbutton node generated by the DS1233. A Schmitt-trigger conditioner converts this signal into the clean logic-level motherboard reset signal RESET_n.

This distinction prevents the RC behavior required by the DS1233 pushbutton interface from being applied directly to ordinary HCT logic inputs.

DS1233 RST
    |
    +-- RESET_RAW_n
            |
            +-- SW_RESET ---- GND
            |
            +-- C_RESET_SW -- GND
            |
            +-- SN74LS14 inverter
                    |
                    +-- RESET_STAGE_H
                            |
                            +-- SN74LS14 inverter
                                    |
                                    +-- RESET_n
                                            |
                                            +-- U_OVERLAY 1/PRE
                                            +-- CPU /RESET LS07 input
                                            +-- CPU /HALT LS07 input

Reset Signal Conditioner

U_RESET_COND is a Texas Instruments SN74LS14N hex Schmitt-trigger inverter. Two inverter stages are cascaded so that the final signal retains the active-low polarity of the original DS1233 reset signal.

RESET_RAW_n = 0
    -> first inverter output = 1
    -> second inverter output = 0
    -> RESET_n asserted

RESET_RAW_n = 1
    -> first inverter output = 0
    -> second inverter output = 1
    -> RESET_n inactive

The Schmitt-trigger input is specifically intended to accept slow or noisy transitions. The first stage therefore accepts the RC-shaped release of RESET_RAW_n, while the second stage receives an ordinary logic transition from the first stage.

Physical Connections

A 100 nF + 1uF ceramic decoupling capacitor shall be placed directly between pins 14 and 7.

The four unused SN74LS14 inputs shall be tied to a defined logic level. Tie unused inputs 5, 9, 11, and 13 to ground. Leave outputs 6, 8, 10, and 12 unconnected.

RESET_RAW_n Loading

RESET_RAW_n is intentionally permitted to transition slowly. Its known loads are the DS1233 itself, the first SN74LS14 Schmitt-trigger input, the manual-reset capacitor, and PCB parasitics.

At a 0.4 V low level, the raw-node load is (5.25 V - 0.4 V) / 3.75 kohm + 0.4 mA = 1.693 mA, below the DS1233's 8 mA rating. At a hypothetical zero-volt output, the same current budget is 1.800 mA. These calculations include the supervisor's internal pull-up; no external pull-up is selected.

RESET_n Logic Levels

The second SN74LS14 stage actively drives RESET_n both high and low. The principal known loads are two SN74LS07 inputs, the SN74HCT74 boot-overlay preset input, and four tied CD74ACT244E inputs at U_DRAM_RESET_BUF. The buffer's four outputs carry the DRAM controller's FAST reset load; it is not placed directly on this net.

The defined RESET_n high-state load is 45 uA: 40 uA for the two LS07 inputs, 1 uA for the HCT74 preset, and 4 uA for the four ACT244 inputs. This leaves 355 uA of the LS14's 400 uA source budget. The low-state load is 0.405 mA: 0.4 mA for the two LS07 inputs, 0.001 mA for the HCT74 preset, and 0.004 mA for the four ACT inputs. This leaves 7.595 mA of the LS14's 8 mA sink budget. Input-current figures retain their individual datasheet test conditions. No switch, capacitor, or pull-up connects directly to this push-pull output.

Boot-Overlay Preset Transition

The SN74HCT74 specifies a maximum input transition time of 500 ns. Connecting the raw DS1233 reset node directly to this input would make compliance dependent on the reset-node RC time constant.

The two-stage SN74LS14 conditioner removes that dependency. U_OVERLAY receives the actively driven RESET_n output rather than RESET_RAW_n.

C_RESET_SW remains 1 nF on RESET_RAW_n. The LS14 datasheet supports slow-input operation but does not specify a guaranteed output rise/fall time. Its 22 ns propagation limit does not prove the HCT74's 500 ns input-transition requirement. Record that evidence gap separately from PCB parasitics. RESET_n includes the HCT74's 10 pF maximum input capacitance plus two unspecified LS07 input capacitances; verify the conditioned output waveform under the final load.

Processor Reset-Node Transition Times

The MC68EC000-specific AC timing table specifies a maximum input transition time of 150 ns for both processor /RESET and /HALT.

These two nodes are open-collector signals and rise through their individual 3.9 kohm pull-up resistors. Their release rates therefore depend on total node capacitance.

The 3.9 kohm values follow from the processor's guaranteed output sink-current limits. They shall not be reduced solely to obtain a faster release edge without repeating the processor-output current calculation.

M68000UM section 10.5, Figure 10-2 uses 0.8 V and 2.0 V as input timing thresholds, with test inputs driven to 0.5 V and 2.4 V. The calculations below screen the 0.8-to-2.0 V release interval. Parameter 32 does not separately label its transition endpoints; retain a full waveform capture rather than treating this threshold-window calculation as complete AC certification. A 10-to-90-percent measurement must state its endpoints and must not be substituted silently.

Rmin = 3900 * 0.95 = 3705 ohm
Rmax = 3900 * 1.05 = 4095 ohm
Vfinal = VCC - Rmax * Ileak
t(0.8 V to 2.0 V) = Rmax * Ctotal * ln((Vfinal - 0.8) / (Vfinal - 2.0))

The LS07 250 uA off-state limit is tested at 30 V. Applying it at the board voltage is a conservative screening assumption, not an additional datasheet guarantee. The current-source leakage model is approximate. No complete worst-case release time can be calculated from the supplied component datasheets alone. Assertion also needs verification: the LS07 specifies propagation delay, not guaranteed output fall time.

Reset Duration Verification

The raw-node timer starts at the DS1233's actual 4.50-to-4.75 V threshold. The CPU, LS14, and LS07 require at least 4.75 V. Retain the conditional startup budget: valid CPU conditions by t0 + 150 ms allow a 100 ms hold before the earliest supervisor release at t0 + 250 ms. External reset during a CPU RESET instruction requires 132 clocks (13.2 us nominal), also covered by that hold when valid at the pins.

Propagation and threshold differences can shorten or lengthen the pulse at a receiver. In general, Wout = Win + drelease - dassert; it is incorrect to claim that adding gates cannot reduce pulse width. The 44 ns two-stage conditioner figure applies only at its test load and 5 V. Verify common /RESET and /HALT assertion rather than using that number as a full board delay bound.

Verification Status

Status

The board-level reset conditioner is frozen: U_RESET_COND is an SN74LS14N, RESET_RAW_n passes through two Schmitt-trigger inverter stages, and the resulting RESET_n is the clean motherboard-reset signal used by ordinary logic.

C_RESET_SW remains frozen at 1 nF on RESET_RAW_n. PCB parasitics are deferred as requested. Post-layout checks cover unspecified LS pin capacitances and output edge limits, peripheral reset loads, and supply-ramp validation. The CPU clock section defines the conservative timing targets.

Sources

Dallas Semiconductor / Analog Devices, DS1233 5V EconoReset; Texas Instruments, SN5414 / SN54LS14 / SN7414 / SN74LS14 Hex Schmitt-Trigger Inverters; Texas Instruments, SN74HCT74 Dual D-Type Flip-Flops With Clear and Preset; and Motorola, M68000 8-/16-/32-Bit Microprocessors User's Manual, MC68EC000 electrical specifications. Local sources: DS1233, pages 2 and 5; SN74LS14, sections 5, 6.3, 6.5, and 6.6 (TI copy); SN74LS07, sections 6.5 and 6.6; SN74HCT74, sections 5.2 and 5.4; M68000UM, sections 5.5, 10.5, 10.13, and 10.14.

14. Post-Layout Verification

The circuit choices and nominal values in this document are final. The checks below require routed-board data or measurements and do not block schematic capture.

The reset switch remains a normally open momentary SPST part selected with the enclosure. C_RESET_SW remains a 1 nF ceramic capacitor, with the exact part left to implementation. The processor MODE pin must be high or unconnected during reset for 16-bit bus mode.

15. Sources

The available MC68EC000 documentation does not give an unambiguous device-specific clock-input table, so this design uses the conservative targets stated in the CPU clock section. The F74 databook Section 1 measurement definitions would improve comparison with its switching table. The LS07 and LS14 datasheets do not specify every pin capacitance or output edge needed for pre-layout timing closure; those checks require measurements on the routed board.