DRAM

1. Scope

This page defines the DRAM-side interface. The address decoder supplies active-low RAM0_REQ_n and RAM1_REQ_n; the DRAM controller turns one request into a DRAM transfer and produces DRAM_DTACK_n. The decoder already excludes CPU-space cycles and suppresses bank 0 while the boot-ROM alias owns the low 128 KiB. See the decoder interface and the memory map.

RAM0_REQ_n and RAM1_REQ_n are timing-independent bank-select levels. The controller reads them and then generates every DRAM strobe itself. Neither line reaches a RAS, CAS, W, or OE input on any part.

The structural SystemVerilog controller and eight-chip testbench are in the repository at code/system-verilog/rtl/dram_controller.sv and code/system-verilog/test/tb_dram_controller.sv. Run make test NAME=dram_controller from code/system-verilog. The simulation uses the existing device models and includes the request-end correction in sections 10, 11, and 14. It expands count-7 decode with equivalent F08/F04 gates because an F20 model is absent; it is not a package-exact schematic or a board timing-closure result.

1.1. 74-Series Logic and System Connections

The 74-series chips form a hardware controller between the MC68EC000 bus and the eight DRAMs. They choose the address presented to memory, remember the requested bank and byte lanes, generate strobes in order, and acknowledge the transfer. A second path schedules refresh through the same sequencer. This overview follows the connections defined in section 10 and the manufacturer references in Sources. Signal names ending in _n are active low.

What each group of chips does

The family letters matter as well as the function number. This design uses FAST TTL (F) for sequencing and glue, TTL-compatible ACT for address muxes and drivers, and HCT for the timer counters. The selected parts and their loads are covered in Electrical Compatibility and Fanout.

Following a CPU transfer through the logic

1. The motherboard decoder produces RAM0_REQ_n or RAM1_REQ_n. It handles the address region, CPU-space exclusion, and boot-ROM overlay. The controller combines the bank request with UDS_n and LDS_n to form DRAM_CPU_REQ, then passes that level through the two F74 synchronizer stages.
2. Arbitration waits for initialization, an idle controller, and no pending refresh. Exactly one bank must be requested. CPU_START loads the F194 transaction register and starts CPU mode. The CPU continues holding address and write data; the F194 stores only bank, byte-lane, and direction qualifiers.
3. The F161 advances the sequence. Its F138 decoders feed the F30 timing-window gates, and glue combines those windows with the saved qualifiers. The F175 control registers capture the results on the controller clock before the strobe buffer drives memory. A phase-decoder output therefore does not directly drive RAS or CAS.
4. The ACT157 muxes initially present the row. The ACT244 strobe buffer drives the selected bank's RAS low to capture that row. Registered address select then switches the muxes to the column. After the settling interval, the buffer drives the selected byte-lane CAS lines low. The read and write timelines give the exact steps.
5. CPU D15..D0 connect directly to the corresponding DRAM DQ pins in both banks, following the nibble wiring table. Data does not pass through the address muxes or control registers. On reads, OE_n permits the selected memory to drive the bus. On writes, the CPU drives data, OE_n stays high, and the controller establishes W_n low before CAS.
6. ACK_ARM passes through the F08 qualification gates to the F74 acknowledgement register. F10 gates combine its output with live AS_n, UDS_n, and LDS_n to produce DRAM_DTACK_n. This feeds U_DTACK_A in the motherboard combining tree, which delivers DTACK_n to the CPU. The local push-pull output must not be joined directly to other acknowledgement outputs.
7. When the CPU negates AS or both byte strobes, the F10 path removes acknowledgement promptly. The synchronized request-end path lets the controller finish closing the cycle and precharging memory. It waits for request clear before accepting another transfer, preventing a held request from executing twice.

At the DRAMs, RAS0_n reaches all four bank 0 parts and RAS1_n reaches all four bank 1 parts. CAS_U_n reaches the two upper-byte parts in each bank; CAS_L_n reaches the two lower-byte parts in each bank. All eight share W_n, OE_n, and the ten multiplexed address lines. RAS chooses the bank and CAS chooses the byte lane during CPU access. CPU A21 contributes to bank decoding, not the multiplexed address. Byte selection uses UDS/LDS rather than a CPU A0 wire.

Refresh, clocks, reset, and the rest of the motherboard

The clock and reset circuit supplies CPU_CLK_DIV2 at 20 MHz, CPU_CLK_10 at 10 MHz, and RESET_n. The ACT244 clock buffer distributes 20 MHz to the controller and buffered 10 MHz to both HCT4040 timers. Its other branches supply ROM_CLK to the firmware-ROM read-delay logic and INT_CLK to the interrupt synchronizer and watchdog. Clock distribution lists the receivers on each branch. The separate reset buffer fans motherboard reset out to the controller; timer reset gates provide the counters' active-high reset signals.

After reset, the startup timer and its F74 synchronizer release initialization. The initialization F161 counts eight CBR cycles before DRAM_INIT_DONE enables CPU service and releases the periodic timer. During normal operation, synchronized Q7 events add credits to the F191. A refresh grant consumes a credit; simultaneous arrival and service leave the count unchanged. Pending credits take priority over a new CPU request at a legal start boundary.

Refresh uses the same phase counter, control registers, and strobe buffer as CPU transfers. Refresh mode asserts both CAS lines before both RAS lines, with W and OE inactive. Each TMS44400 uses its internal CBR address counter, so no external refresh-row address mux is needed. Refresh does not drive CPU data or generate a CPU acknowledgement. An arriving CPU DRAM request waits for refresh and precharge to finish. Refresh Architecture and Reset Behavior detail these paths.

ROM, VGA, and the other memory-mapped peripherals use their own selects and acknowledgement paths on the shared CPU bus; their register accesses do not pass through this DRAM sequencer. The decoder separates device selections and the motherboard DTACK tree combines completion signals. All controller and DRAM packages connect to motherboard +5 V and ground, with local bypass and bank capacitors as specified in PCB and Decoupling Notes.

2. Parts and Capacity

A TMS44400DJ-70 is a 5 V, 1,048,576 x 4-bit DRAM. Four parts make one 1M x 16 bank, or 2 MiB. The organization, ten address inputs, and -70 speed grade are from the TMS44400 data sheet, pages 1 and 8-10.

All four parts in a bank share the multiplexed address inputs. The two banks may share that address bus because only the selected bank receives an active RAS pulse.

3. Data-Bus Organization

Each x4 part supplies one nibble. All four parts in a selected bank receive the same row and column address. Two parts form the upper byte and two form the lower byte. Each byte pair has its own active-low CAS signal, so an MC68EC000 byte transfer selects only the requested lane.

The completed controller has separate RAS0_n and RAS1_n outputs, but the banks share CAS_U_n and CAS_L_n. All eight parts share W_n and OE_n. The reference designators in the table are the required schematic names.

In each detailed-wiring row, the four entries are the connections for DQ1, DQ2, DQ3, and DQ4, in that order. On the 26-pin DJ (SOJ) package those pins are 1, 2, 24, and 25, from the pinout on page 1 of the TMS44400 data sheet.

A word transfer drives both byte lanes; a byte transfer drives only the lane named by its CPU strobe. The controller converts the CPU byte strobes into the shared CAS signal for the selected lane. Both banks sit on the CPU data bus at once, but only the bank with an active RAS can enable its outputs during a read.

4. Byte-Lane and CAS Organization

The MC68EC000 data bus has two independently selected byte lanes. Two x4 DRAM parts in each bank form each eight-bit lane.

Upper byte: D15..D8  selected by UDS_n
Lower byte: D7..D0   selected by LDS_n

The banks have separate RAS signals but share the byte-lane CAS signals. An asserted shared CAS cannot select the other bank during a CPU access because that bank's RAS remains high.

CAS_U_n
  +-- U_DRAM0_UH CAS
  +-- U_DRAM0_UL CAS
  +-- U_DRAM1_UH CAS
  +-- U_DRAM1_UL CAS

CAS_L_n
  +-- U_DRAM0_LH CAS
  +-- U_DRAM0_LL CAS
  +-- U_DRAM1_LH CAS
  +-- U_DRAM1_LL CAS

The TMS44400 keeps its outputs at high impedance until RAS, CAS, and output enable are all active. This permits both banks to share CAS_U_n and CAS_L_n while RAS0_n and RAS1_n select the active bank. See pages 3 and 4 of the TMS44400 data sheet.

"Sequenced active" means the strobe only selects a lane; the CAS edge comes later, from the controller. When the controller accepts a DRAM request, it captures both byte strobes and the transfer direction. The captured values form these active-high lane requests:

UPPER_REQ = NOT UDS_n
LOWER_REQ = NOT LDS_n

During the column phase, the controller asserts only the shared CAS signals selected by those captured requests. During CBR refresh, it ignores the captured requests and asserts both CAS signals before asserting both RAS signals.

A normal cycle returns both CAS signals high before another RAS sequence begins. For the -70 part, CAS must remain low for at least 18 ns and high for at least 10 ns. CAS must fall at least 20 ns after RAS. The listed 52 ns tRCD maximum is a condition for claiming the 70 ns tRAC access time, not a maximum legal delay. These are tCAS, tCP, and tRCD from pages 9 and 10 of the data sheet.

The shared OE_n signal is low only during the read-data window. It remains high during writes, idle, reset, initialization, and CBR refresh. Either CAS returning high or OE_n returning high disables the DRAM outputs.

5. Bank Selection

Main memory has two independently selected 2 MiB DRAM banks. Each bank contains four TMS44400DJ-70 parts and has its own row-address strobe.

Bank 0:  4 x TMS44400DJ-70  $000000-$1FFFFF  RAS = RAS0_n
Bank 1:  4 x TMS44400DJ-70  $200000-$3FFFFF  RAS = RAS1_n

RAS0_n connects to the RAS input of all four bank 0 parts. RAS1_n connects to the RAS input of all four bank 1 parts. The global address decoder supplies the already-qualified requests RAM0_REQ_n and RAM1_REQ_n; they identify the target bank but do not directly drive DRAM RAS.

RAM0_REQ_n  --> DRAM controller --> RAS0_n
RAM1_REQ_n  --> DRAM controller --> RAS1_n

The controller first drives the row address, then asserts RAS so the selected DRAM parts latch it. It may assert RAS for only one bank during a CPU transaction; the other bank remains inactive.

"Sequenced active" means that an active request does not cause an immediate RAS edge. The controller must establish the row address and meet the TMS44400 timing limits first.

Bank 0 overlay suppression is already part of RAM0_REQ_n. The DRAM controller does not need the overlay state: while the firmware alias occupies $000000-$01FFFF, the decoder does not issue a bank 0 request for that range.

Both banks share the multiplexed DRAM address bus, CPU data bus, and byte-lane CAS signals. The separate RAS signals isolate the banks during CPU accesses.

Refresh does not use CPU requests. Each CBR refresh asserts both byte-lane CAS signals, then both RAS signals, so all eight parts refresh one internal row together.

6. Address Multiplexing

The CPU is byte addressed. In this 16-bit system, A0 does not select a DRAM location; UDS_n and LDS_n select the byte lanes. Each 2 MiB bank has 2^20 16-bit words, so its word address is CPU A1..A20. The DRAM latches a ten-bit row on RAS and a ten-bit column on CAS.

The address multiplexer must hold the row long enough for the RAS edge, then change to the column before CAS falls. CPU bits above A20 select the bank and do not enter the DRAM address multiplexer.

7. Row and Column Multiplexer Architecture

The TMS44400 uses a multiplexed address bus, so the motherboard must choose either the ten-bit CPU row address or the ten-bit CPU column address before driving DRAM A0..A9.

ROW:    CPU A1..A10
                  \
                   +-- 2:1 mux --> DRAM A0..A9
                  /
COLUMN: CPU A11..A20

Use three Texas Instruments CD74ACT157E parts. Each is a 16-pin PDIP containing four non-inverting 2:1 multiplexers, giving twelve channels for the ten required address bits. The 74ACT157 function in a through-hole DIP was a standard catalog part before the project's 1994 component cutoff. The CD74ACT157 data sheet (TI SCHS340D) lists CD74ACT157E as the PDIP orderable part, specifies TTL-compatible inputs (2 V high, 0.8 V low), and rates the outputs for a load of 50 pF or less.

All three parts share DRAM_ADDR_COL. A low selects the row input; a high selects the column input.

Tie each active-low mux enable low. Disabling a 157 drives its outputs low rather than isolating the bus, so it is not useful for DRAM address control. Tie both inputs of each unused channel to a defined logic level and leave its output open.

Each used output drives the matching address input on all eight DRAM parts. The TMS44400 data sheet specifies 5 pF maximum address-input capacitance per part, so the DRAM input load is at most 40 pF per mux output before socket, trace, and probe capacitance.

The controller changes DRAM_ADDR_COL only after the row address has met the TMS44400 tRAH hold time following the RAS edge. It must then allow the mux and board path to settle before CAS falls. The RAS-to-CAS interval must be at least 20 ns. Exceeding the listed 52 ns tRCD access-time condition is legal, but read completion must then use the column-address and CAS access times instead of assuming 70 ns from RAS.

8. DRAM Controller Requirements

The DRAM controller converts a qualified motherboard RAM request into one complete electrical transaction for the selected TMS44400 bank. It also initializes and refreshes both banks without firmware help.

Interface

The TMS44400 data sheet names the physical control pins RAS, CAS, W, and OE; each is active low. The _n suffix records that polarity in the motherboard net name.

CPU access sequence

Every accepted CPU request follows this order:

1. Capture the bank, byte strobes, and transfer direction.
2. Drive the row address through the address mux.
3. Assert RAS for only the requested bank.
4. Meet the row-address hold time, then select the column address.
5. Assert the shared CAS signal or signals for the captured byte lanes.
6. Apply the read or early-write control sequence.
7. Wait until all DRAM and CPU timing requirements are satisfied.
8. Assert DRAM_DTACK_n and hold it low until AS_n returns high.
9. Return CAS, RAS, W_n, and OE_n to their idle levels.
10. Complete RAS precharge before starting another operation on that bank.

The interface fixes the order of these steps, not the state count. The sequencer may spend more than one state on any step, provided it meets the electrical limits and runs only one DRAM operation at a time.

Bank and byte-lane invariants

A normal CPU access asserts RAS for only the requested bank. The other bank stays inactive even while a shared byte-lane CAS is low. The controller uses RAM0_REQ_n and RAM1_REQ_n only to choose which RAS to sequence.

Bank 0 access: RAS0_n sequenced active, RAS1_n high
Bank 1 access: RAS1_n sequenced active, RAS0_n high

UDS_n low:     upper byte requested
LDS_n low:     lower byte requested
both low:      both bytes requested

The captured byte strobes qualify the shared CAS signals during the column phase only.

Read completion

The controller asserts DRAM_DTACK_n only after the requested data is valid at the MC68EC000 pins. The timing budget must include the TMS44400 access time, output and board loading, trace delay, and any buffer or acknowledgement logic delay.

At 10 MHz, MC68EC000 timing parameter 27 requires data to be valid at least 5 ns before the sampling clock-low edge. Parameter 47 requires an asynchronous DTACK input to meet 5 ns setup to its sampling clock edge. The final timing analysis must show both margins. These limits are in the M68000 User's Manual, pages 10-24 and 10-25.

Write completion

The baseline controller uses the TMS44400 early-write cycle: drive valid write data and assert W_n before the selected CAS signal falls. Keep the address, data, RAS, CAS, and write control valid for all setup, pulse-width, and hold requirements before acknowledging the transfer. The applicable -70 limits appear in the timing table on this page and in Figure 5 of the TMS44400 data sheet.

Refresh and serialization

A refresh and a CPU access never overlap. A due refresh waits for an active CPU transaction to complete, then runs before the controller accepts another request. The refresh request remains pending until it is serviced.

• Schedule one CBR refresh on each 12.8 us timer event.
• Assert both shared CAS signals before asserting both RAS signals.
• Keep W_n and OE_n high throughout refresh.
• Meet the CBR pulse, hold, cycle, and precharge requirements.
• Prove that arbitration cannot violate 1,024 refreshes per 16 ms.

Fast Page Mode is not required. The baseline controller closes the complete row/column cycle and performs precharge after every CPU transaction.

Reset outputs

Motherboard RESET_n resets the DRAM controller. The processor's bidirectional reset pin is a different net, so a CPU RESET instruction does not reset this controller.

During RESET_n assertion:
DRAM_ADDR_COL = low
RAS0_n        = high
RAS1_n        = high
CAS_U_n       = high
CAS_L_n       = high
W_n           = high
OE_n          = high
DRAM_DTACK_n  = high

On release, the controller runs the 200 us pause and eight-cycle initialization sequence before it accepts a CPU request. Reset behavior covers the reset domain, transaction abort, retention, and the power-up sequence in full.

Failure behavior

The controller asserts DRAM_DTACK_n only for a transaction it accepted and completed. If it does not complete a request, DRAM_DTACK_n stays high and the motherboard timeout ends the CPU cycle with BERR_n.

9. Sequencer Clock Selection

The DRAM controller uses CPU_CLK_DIV2, the existing 20 MHz first-stage divider output. Its nominal period is 50 ns. This clock is phase-related to CPU_CLK_10 because the second divider stage derives the CPU clock from the same node.

DRAM sequencer clock = CPU_CLK_DIV2
nominal frequency    = 20 MHz
nominal state period = 50 ns
architecture status  = frozen
electrical status    = verify buffered branches on the assembled board

U_DRAM_CLK_BUF, a CD74ACT244E, isolates all controller clock loads from the motherboard divider. Its connections and assembled-board limits are fixed below.

TMS44400DJ-70 timing basis

The TMS44400 timing-table note says the listed tRAD and tRCD maxima exist only to ensure the specified RAS access time. They are not maximum legal delays. Once either condition is exceeded, read completion must use tAA, tCAC, and tOEA rather than assuming data is valid 70 ns after RAS falls.

Conservative state policy

A nominal 50 ns state does not prove a 50 ns minimum requirement. Clock tolerance, propagation delay, and skew reduce the interval seen at the pins. Requirements equal to one nominal state therefore receive an extra state unless a complete timing analysis proves sufficient margin.

RAS precharge:  tRP  = 50 ns minimum  -> allocate 2 ticks
RAS active:     tRAS = 70 ns minimum  -> allocate at least 2 ticks
CAS active:     tCAS = 18 ns minimum  -> allocate at least 1 tick

During a normal completed CPU transaction, RAS and CAS may remain low longer while the CPU samples DRAM_DTACK_n and releases its bus strobes. The sequencer must still stay below the TMS44400 maximum active times.

Row-to-column sequence

The baseline reserves a complete state before RAS and another complete state between selecting the column and asserting CAS:

select row address
    -> wait 1 tick
assert selected RAS
    -> wait 1 tick
select column address
    -> wait 1 tick
assert selected CAS

The CD74ACT157 select-to-output delay is 14.5 ns maximum at a 50 pF load over its full rated temperature range. One 50 ns state leaves additional time for interconnect only if the total mux load remains within that test condition. The existing 40 pF DRAM input load leaves 10 pF for sockets, routing, and probing before a different timing proof or extra buffering is required.

This sequence deliberately exceeds the tRAD and tRCD conditions for the 70 ns RAS access time. After CAS falls, the earliest acknowledgement state must allow the 35 ns tAA, 18 ns tCAC, and 18 ns tOEA maxima plus board and acknowledgement-path delay. Add another wait state if the completed path does not leave the CPU setup margins documented above.

MC68EC000 timing basis

Use only the MC68EC000-specific table in M68000UM section 10.14. The general read/write table explicitly excludes this processor. At 10 MHz, the applicable values include:

The asynchronous acknowledgement interface lets the controller extend the CPU cycle until the DRAM data and control timing are ready. It does not have to finish within a fixed number of CPU states.

10. Controller Implementation

The controller uses only through-hole 74-series logic available by 1994. A synchronous phase counter and two decoders make the phase terms. Two SN74F175N registers hold every timing-sensitive DRAM control. A CD74ACT244E drives the external control nets. Combinational next-state logic never drives a DRAM pin directly.

Local data sheets cover the SN74F175, SN74F138, SN74F04, SN74F00, SN74F02, SN74F20, SN74F30, SN74F86, and CD74ACT244. The 1980 Fairchild FAST Data Book documents the 74F191PC. The locally archived 1989 Philips 74F194 specification gives the transaction register's complete timing.

Clock distribution

On U_DRAM_CLK_BUF, ground output-enable pins 1 and 19. Pin 2 receives CPU_CLK_DIV2, and pin 18 produces DRAM_CLK_ROOT. Pins 4, 6, 8, and 11 receive that root; pins 16, 14, 12, and 9 produce DRAM_CLK_A through DRAM_CLK_D. Pin 13 receives CPU_CLK_10, and pin 7 produces DRAM_CLK_10. Pin 15 receives DRAM_CLK_10 and pin 5 produces ROM_CLK, the buffered clock for the firmware ROM read-delay flip-flops defined in firmware-rom.html. Pin 17 receives DRAM_CLK_10 and pin 3 produces INT_CLK, the buffered clock for the interrupt-logic synchronizer and watchdog defined in interrupts.html. Pins 10 and 20 are ground and +5 V. This uses all eight channels of the buffer.

DRAM_CLK_A -> U_DRAM_PHASE, U_DRAM_MODE, U_DRAM_CTL_A, U_DRAM_CTL_B
DRAM_CLK_B -> both U_DRAM_REQ_SYNC clocks, U_DRAM_TX, U_DRAM_ACK
DRAM_CLK_C -> U_REFRESH_SYNC, U_REFRESH_CREDIT, U_DRAM_INIT_CNT
DRAM_CLK_D -> both U_INIT_SYNC clocks
DRAM_CLK_10 -> U_STARTUP_DIV, U_REFRESH_DIV, U_DRAM_CLK_BUF pin 15, U_DRAM_CLK_BUF pin 17
ROM_CLK     -> four SN74AHCT74N clock inputs in the firmware ROM read-delay chain
INT_CLK     -> two SN74LS174 and one CD74HCT4040E clock input in the interrupt logic
            -> one SN74HCT74N clock input in the MFP clock divider
            -> one SN74F04N input in the RTC local clock buffer
MFP_CLK_5   -> one SN74F04N input in the MIDI local clock buffer
            -> one CD74HCT164E clock input in the floppy bus adapter

The phase counter and control registers share one branch, so branch skew cannot violate their hold relationship. Measure all clock branches at the receiving pins on the assembled board.

DRAM_CLK_10 gains two CD74ACT244E input loads at pins 15 and 17; it now drives the two divider counters and those two buffer inputs. ROM_CLK on pin 5 drives four firmware flip-flop clocks; INT_CLK on pin 3 drives three interrupt clock inputs and the first stage of the MFP clock divider. Those known INT_CLK loads total 40 pF. The RTC adds one SN74F04 input; its input capacitance is not specified. The RTC layout checks therefore require the complete routed branch to remain within the CD74ACT244E 50 pF timing-analysis load. MFP_CLK_5 separately drives the MFP divider's second stage, one SN74F04 input in the MIDI clock buffer, and one CD74HCT164E clock input in the floppy response sequencer. CPU_CLK_10 loading in Clock and Reset is unchanged.

Reset distribution

U_DRAM_RESET_BUF prevents the DRAM controller's FAST clear inputs from loading the motherboard LS14 reset conditioner. Ground output-enable pins 1 and 19. Connect motherboard RESET_n to input pins 2, 4, 6, and 8; output pins 18, 16, 14, and 12 are DRAM_RESET_A_n through DRAM_RESET_D_n. Tie input pins 11, 13, 15, and 17 to GND and leave output pins 9, 7, 5, and 3 open.

DRAM_RESET_A_n -> U_DRAM_REQ_SYNC, U_DRAM_TX, U_DRAM_ACK
DRAM_RESET_B_n -> U_DRAM_PHASE, U_DRAM_MODE, U_DRAM_CTL_A, U_DRAM_CTL_B
DRAM_RESET_C_n -> U_REFRESH_SYNC, U_REFRESH_CREDIT, U_DRAM_INIT_CNT
DRAM_RESET_D_n -> U_INIT_SYNC, U_DRAM_INV_C, U_DRAM_NAND reset input

Each branch drives at most four FAST inputs. References to RESET_n on controller pins below mean the branch assigned in this table, not a direct connection to the motherboard net. The four ACT inputs add only 4 uA maximum DC load to motherboard reset. A four-input FAST branch draws at most 80 uA HIGH or 2.4 mA LOW, within the ACT244's 24 mA source and sink ratings.

Phase counter and decode

U_DRAM_PHASE uses pin 2 for DRAM_CLK_A, pin 1 for RESET_n, and grounded parallel inputs on pins 3 through 6. Pins 7 and 10 receive PHASE_COUNT_ENABLE and pin 9 receives PHASE_LOAD_n. Pins 14, 13, 12, and 11 are PHASE_QA through PHASE_QD. Leave pin 15 open. Pins 8 and 16 are ground and +5 V.

RUN = CPU_BUSY OR REFRESH_BUSY
REFRESH_DONE = REFRESH_BUSY AND PHASE_5
PHASE_LOAD_n = RUN AND NOT REFRESH_DONE
PHASE_COUNT_ENABLE = REFRESH_BUSY OR (CPU_BUSY AND PHASE_9_n)

Both SN74F138N decoders take PHASE_QA, PHASE_QB, and PHASE_QC on pins 1, 2, and 3. Pin 5 is low and pin 6 receives RUN. Pin 4 receives PHASE_QD on the low decoder and PHASE_QD_n on the high decoder. Outputs pins 15, 14, 13, 12, 11, 10, 9, and 7 are the active-low phase terms in ascending order. Pins 8 and 16 are ground and +5 V.

CPU_RAS_WINDOW = phase 0 through 5
CPU_COL_WINDOW = phase 1 through 5
CPU_CAS_WINDOW = phase 2 through 5
CBR_CAS_WINDOW = phase 0 through 3
CBR_RAS_WINDOW = phase 1 through 2

Each window is the output of its named SN74F30N. Connect the listed active-low phase outputs to the NAND inputs and tie the remaining inputs high. Each package contains one functional gate.

Mode and output equations

U_DRAM_MODE stores CPU_BUSY, REFRESH_BUSY, and CPU_REQUEST_ENDED in flip-flops 1 through 3. Their D inputs are pins 4, 5, and 12; their Q outputs are pins 2, 7, and 10. Pin 11 supplies CPU_REQUEST_ENDED_n for acknowledgement qualification. Tie unused D input pin 13 low and leave its outputs open. Pin 1 is RESET_n, pin 9 is DRAM_CLK_A, and pins 8 and 16 are ground and +5 V.

IDLE = NOT (CPU_BUSY OR REFRESH_BUSY)
VALID_CPU_REQUEST = REQ_SYNC2 AND (BANK0_ACTIVE XOR BANK1_ACTIVE)

INIT_START = IDLE AND INIT_DELAY_DONE AND NOT DRAM_INIT_DONE
REFRESH_SERVICE = IDLE AND DRAM_INIT_DONE AND REFRESH_PENDING
CPU_START = IDLE AND DRAM_INIT_DONE AND NOT REFRESH_PENDING
            AND VALID_CPU_REQUEST
START_REFRESH = INIT_START OR REFRESH_SERVICE

CPU_REQUEST_ENDED_D = CPU_BUSY AND (CPU_REQUEST_ENDED OR NOT REQ_SYNC2)
CPU_BUSY_D = CPU_START
             OR (CPU_BUSY AND
                 (PHASE_9_n OR (REQ_SYNC2 AND NOT CPU_REQUEST_ENDED)))

INIT_LAST = INIT_COUNT_QA AND INIT_COUNT_QB AND INIT_COUNT_QC
            AND NOT INIT_COUNT_QD
REFRESH_BUSY_D = START_REFRESH
                 OR
                 (REFRESH_BUSY
                  AND
                  (PHASE_5_n OR (NOT DRAM_INIT_DONE AND NOT INIT_LAST)))

U_DRAM_CTL_A stores active-high RAS0, RAS1, upper CAS, and lower CAS in flip-flops 1 through 4. D inputs are pins 4, 5, 12, and 13. Complementary outputs pins 3, 6, 11, and 14 are the active-low pre-driver signals.

U_DRAM_CTL_B stores W_ACTIVE, OE_ACTIVE, DRAM_ADDR_COL, and ACK_ARM. D inputs are pins 4, 5, 12, and 13. Use pin 3 as W_n_PRE, pin 7 as OE_ACTIVE, pin 10 as DRAM_ADDR_COL_PRE, and pin 15 as ACK_ARM. Leave unused outputs open. Both control registers use RESET_n on pin 1 and DRAM_CLK_A on pin 9.

RAS0_ACTIVE_D = (CPU_BUSY AND CPU_RAS_WINDOW AND NOT TX_BANK1)
                OR (REFRESH_BUSY AND CBR_RAS_WINDOW)
RAS1_ACTIVE_D = (CPU_BUSY AND CPU_RAS_WINDOW AND TX_BANK1)
                OR (REFRESH_BUSY AND CBR_RAS_WINDOW)
CAS_U_ACTIVE_D = (CPU_BUSY AND CPU_CAS_WINDOW AND TX_UPPER)
                 OR (REFRESH_BUSY AND CBR_CAS_WINDOW)
CAS_L_ACTIVE_D = (CPU_BUSY AND CPU_CAS_WINDOW AND TX_LOWER)
                 OR (REFRESH_BUSY AND CBR_CAS_WINDOW)
W_ACTIVE_D = CPU_BUSY AND CPU_RAS_WINDOW AND TX_WRITE
OE_ACTIVE_D = CPU_BUSY AND CPU_CAS_WINDOW AND NOT TX_WRITE
DRAM_ADDR_COL_D = CPU_BUSY AND CPU_COL_WINDOW
ACK_ARM_D = CPU_BUSY AND NOT CPU_REQUEST_ENDED
            AND REQ_SYNC2 AND (PHASE_3 OR ACK_ARM)
OE_n_PRE = NOT (OE_ACTIVE AND DRAM_CPU_REQ)

These equations are the glue-logic netlist. Use the named SN74F08N packages for two-input products and the SN74F32N packages for sums. Use SN74F04N for written inversions, SN74F02N for IDLE, SN74F86N for XOR terms, SN74F00N for OE_n_PRE, and SN74F20N followed by an inverter for INIT_LAST. Assign gates in equation order, starting with gate 1 of the first package. Tie unused gate inputs low and leave unused outputs open.

External control driver

Ground enable pins 1 and 19. Pins 10 and 20 are ground and +5 V. The ACT driver has a 9.6 ns maximum data-to-output delay over -55 C to +125 C at 5 V and 50 pF. Its 24 mA source and sink ratings exceed all DRAM control-net DC loads. The known 56 pF loads on W_n and OE_n exceed the 50 pF switching condition, so measure those two delays and edges on the assembled board.

Cutoff rule

Every selected function and through-hole ordering code appears in a manufacturer book or specification published by 1994. A later data sheet revision may document electrical limits for the same function, but it does not authorize a post-1994 part or surface-mount package.

11. CPU Request Capture and Controller Start

The controller does not start a DRAM cycle on a bank-select request alone. It waits until at least one MC68EC000 byte strobe is low, so the transfer width and byte lane are known before it accepts the cycle.

RAM_SELECTED = (NOT RAM0_REQ_n) OR (NOT RAM1_REQ_n)
BYTE_STROBE  = (NOT UDS_n) OR (NOT LDS_n)
DRAM_CPU_REQ = RAM_SELECTED AND BYTE_STROBE

Waiting for a byte strobe matters most on writes. At 10 MHz, the MC68EC000 holds R/W low at least 50 ns before a data strobe falls and holds write data valid at least 30 ns before that edge. The controller therefore waits for UDS_n or LDS_n instead of starting from an address decode caused by AS_n alone. These are timing parameters 22 and 26 in section 10.14 of the M68000 User's Manual.

Request synchronizer

Both flip-flops in U_DRAM_REQ_SYNC, an SN74F74N, synchronize DRAM_CPU_REQ to the 20 MHz DRAM_CLK_B clock. Both stages sample on a rising edge. Their preset inputs are tied high, and motherboard RESET_n drives both active-low clear inputs.

                         U_DRAM_REQ_SYNC
DRAM_CPU_REQ  ---D  stage 1  Q---D  stage 2  Q--- REQ_SYNC2
                   REQ_SYNC1

CLK, both stages = DRAM_CLK_B
PRE, both stages = high
CLR, both stages = RESET_n

The first stage may sample a changing request. The controller uses only REQ_SYNC2, giving the first stage one 50 ns clock period to settle. This reduces metastability risk; it does not make the risk mathematically zero. The CPU keeps its address, strobes, direction, and write data stable while it waits for a cycle termination signal, so the synchronizer latency does not lose the request.

The SN74F74 data sheet requires inactive preset and clear inputs to be stable at least 2 ns before a rising clock edge. Reset release may violate that recovery time on the first edge. The initialization state machine must ignore the synchronizer until at least two clean 20 MHz edges have occurred after RESET_n rises. The existing 200 us DRAM initialization delay provides much more time than this requirement.

Transaction qualifier register

On an accepted request, U_DRAM_TX, a Philips N74F194N, stores the four values needed after the controller leaves its armed idle state. The address and write data are not stored here: the MC68EC000 continues to drive them until the controller returns DRAM_DTACK_n and the CPU ends the bus cycle.

A valid normal request has exactly one active bank-select input. If both bank requests are low, the controller must not start a cycle or assert DRAM_DTACK_n; the motherboard timeout will report the decode fault. Because valid bank requests are mutually exclusive, one stored bank bit is sufficient.

The N74F194N is used as a parallel register, not as a shifter. Tie DSR pin 2 and DSL pin 7 low. Connect CP pin 11 to DRAM_CLK_B, MR pin 1 to RESET_n, pin 8 to ground, and pin 16 to +5 V. Drive S0 pin 9 and S1 pin 10 from CPU_START so the register loads on the accepting edge and holds its value on every other edge.

Generate CPU_START from the registered controller state, REQ_SYNC2, and the refresh arbiter. Do not gate the clock. The Philips data sheet requires 9 ns of mode-input setup, 4 ns of parallel-data setup, and 1 ns of parallel-data hold over the commercial temperature range. The synchronized request supplies settling time for the raw bank, strobe, and direction paths, but the schematic timing analysis must still prove these three limits at U_DRAM_TX.

Connect the N74F194N active-low master reset to RESET_n. It requires 8 ns of recovery before the next rising clock edge. As with the request synchronizer, the controller ignores its outputs during initialization. A CPU RESET instruction does not assert motherboard RESET_n and does not clear either register.

Philips specified N74F194N as the 16-pin plastic DIP ordering code in its 1989 74F194 product specification, so the exact part and through-hole suffix predate the project's 1994 cutoff. Its commercial limits include 8 ns maximum clock-to-Q, 9 ns mode setup, 4 ns data setup, 1 ns hold, and 8 ns reset recovery.

Start, refresh, and re-arm rules

The controller asserts CPU_START only when all of these are true:

state = IDLE_ARMED
REQ_SYNC2 = 1
exactly one of RAM0_REQ_n and RAM1_REQ_n is low
refresh arbiter grants the DRAM to the CPU

On that rising edge, U_DRAM_TX loads the qualifiers and the state machine leaves IDLE_ARMED. The address mux remains in row mode. A later state asserts the selected RAS; acceptance itself does not create a DRAM control edge.

The request is a level, not a pulse. If refresh owns the controller, the CPU has not received DRAM_DTACK_n and continues to hold the bus cycle. REQ_SYNC2 therefore remains high until the refresh finishes, so a separate one-entry request queue is not needed.

After finishing a CPU transaction, enter WAIT_REQUEST_CLEAR. Return to IDLE_ARMED only after observing REQ_SYNC2 low, remembering that observation in CPU_REQUEST_ENDED even if a new request arrives before phase 9. The remembered end releases CPU ownership when precharge finishes; it clears when that ownership ends. This prevents one extended cycle from executing twice without losing the next cycle. The 105 ns minimum inter-cycle strobe gap is exercised by the controller simulation. Merely waiting for a low synchronized request in phase 9 can miss that gap.

12. Read Cycle

The baseline controller performs one complete random-access DRAM cycle for each CPU read. It does not use Fast Page Mode. A read begins only after the request synchronizer has reported a request and U_DRAM_TX has captured the bank and byte-lane qualifiers. W_n remains high for the entire read.

Sequencer timeline

The offsets below are nominal times from the 20 MHz edge that asserts the selected RAS. Request acceptance occurs earlier, while RAS and CAS are still high, so the row address receives a complete settling state before the first edge shown here.

Only one bank RAS falls. TX_UPPER permits CAS_U_n to fall, and TX_LOWER permits CAS_L_n to fall. An unrequested lane keeps CAS high. The other bank keeps RAS high, so it cannot drive the shared data bus even though both banks share CAS and OE_n.

Row and column address timing

The TMS44400DJ-70 specifies tASR = 0 ns for row-address setup and tRAH = 10 ns for row-address hold after RAS falls. This controller provides a full state before RAS and keeps the mux in row mode for another nominal 50 ns after RAS falls.

At 50 ns the controller selects CPU A11..A20 as the DRAM column. It then waits one state before asserting CAS. The DRAM permits tASC = 0 ns, but the reserved interval allows the CD74ACT157E and board path to settle. The mux data sheet specifies 14.5 ns maximum select-to-output delay only at its stated 50 pF test load, so the completed address load must still remain within that condition or receive a separate timing analysis.

Data-valid timing

CAS falls 100 ns after RAS, which exceeds the 52 ns tRCD condition for claiming the 70 ns tRAC access time. Read readiness is therefore based on the column-address, CAS, and output-enable paths.

These nominal allocations are measured at sequencer state boundaries, not at the DRAM or CPU pins. Clock tolerance, controller propagation, trace delay, DRAM loading, and acknowledgement-logic delay consume part of the margin. READ_READY at 150 ns is therefore the earliest permitted internal ready state, not by itself proof that the CPU may be acknowledged.

The published access times use the TMS44400 data sheet's 100 pF output load circuit, including probe and fixture capacitance. The load on each DQ pin is one CPU data input plus its route and probe. Keep that total within the test condition or recalculate the read-data delay. The limits and load circuit are on pages 8-11 of the TMS44400 data sheet.

CPU acknowledgement

At 10 MHz, the MC68EC000 requires read data to be valid at least 5 ns before its sampling clock-low edge. An asynchronous DTACK also needs 5 ns of setup to the clock edge on which it is recognized. After READ_READY, the acknowledgement register described below samples its gated data input (ACK_D, which equals ACK_ARM while the cycle is active) on the following 20 MHz rising edge. The completed data and acknowledgement paths must still leave both margins at the CPU pins. Check them against parameters 27 and 47 in section 10.14 of the M68000 User's Manual.

Output release and cycle close

Once the raw CPU DRAM request ends, OE_n must return high without waiting for that change to pass through both synchronizer stages. The required active-low qualification is:

OE_n = SEQUENCED_OE_n OR (NOT DRAM_CPU_REQ)

Thus a missing raw request forces OE_n high even while the sequencer still holds its read state. The implementation must be free of a low-going hazard when the raw bank and strobe terms change. The TMS44400DJ-70 specifies tOEZ = 18 ns maximum from OE high to an undriven output. The MC68EC000FN10 provides at least 105 ns with AS_n and its data strobes negated between bus cycles, leaving time for the DRAM to release the shared data bus.

The DRAM cycle closes on the phase-6 edge, independent of the CPU request level. RAS, CAS, and OE return high and the address mux returns to row mode. ACK_ARM remains high until REQ_SYNC2 clears, so the CPU still sees a valid acknowledgement even though the DRAM row is closed. This separates the DRAM's 10 us maximum strobe time from the motherboard's longer bus timeout.

register acknowledgement
    -> hold data and strobes for two more 20 MHz ticks
    -> return OE, CAS, and RAS high at the phase-6 edge
    -> return the address mux to row mode
    -> keep RAS high for 2 ticks
    -> remember REQ_SYNC2 low in CPU_REQUEST_ENDED; clear ACK_ARM
    -> leave CPU ownership at phase 9, even if the next request is already high
    -> return to IDLE_ARMED

Two 20 MHz precharge states provide 100 ns nominal against the 50 ns minimum tRP. The ordinary acknowledged path also keeps RAS and CAS below 350 ns in this sequence, far under their 10 us maximum low times. A hung CPU request can hold the controller in phase 9, but all DRAM strobes are inactive there.

13. Write Cycle

The baseline controller performs one complete random-access DRAM cycle for each CPU write. It does not use Fast Page Mode. The TMS44400 uses its early-write mode: W_n falls before the selected CAS, and OE_n remains high throughout the transaction.

W_n connects to all eight DRAM parts. It does not select a bank or byte lane. The stored bank bit selects RAS0_n or RAS1_n, while TX_UPPER and TX_LOWER select CAS_U_n and CAS_L_n. A part writes only when its RAS, CAS, and W inputs are active.

W_n shared by all eight parts
RAS0_n or RAS1_n selects the bank
CAS_U_n and CAS_L_n select the byte lanes
OE_n remains high

The TMS44400 data sheet states that an early write keeps the data outputs at high impedance regardless of OE. Holding OE_n high also prevents an unintended read-output interval if control edges are skewed.

Sequencer timeline

The offsets below are nominal times from the 20 MHz state boundary that asserts the selected RAS and W_n. Request acceptance occurs earlier, with the address mux in row mode, so the row address and CPU write data have already had time to settle.

Address timing

The address sequence matches the read cycle. The controller holds the row selection for one nominal 50 ns state after RAS falls, exceeding the 10 ns tRAH minimum. It then selects the column and waits another complete state before CAS falls. The DRAM permits tASC = 0 ns, but the reserved state is still required for the CD74ACT157E and board path.

Early-write timing

In the baseline sequence, W falls at the RAS boundary and nominally 100 ns before CAS. CAS then remains low for at least one complete state before WRITE_READY. The table includes the full-cycle limits as well as those referenced directly to the CAS edge.

The tDS and tDH references are the later active edge of CAS or W. W falls first in this design, so the selected CAS falling edge is the controlling write-data event. The values and Figure 5 are on pages 9 and 12 of the TMS44400 data sheet.

CPU write-data timing

The MC68EC000FN10 guarantees write data valid at least 30 ns before a data strobe falls. The controller waits for a byte strobe and then passes the request through two 20 MHz synchronizer stages before the transaction can start. CPU write data is therefore stable well before the DRAM CAS edge.

After acknowledgement, the CPU keeps write data valid for at least 30 ns after AS and its data strobes rise. CAS fell at least one nominal state before acknowledgement became eligible, so the TMS44400's 15 ns tDH requirement has already elapsed before the CPU can end the cycle. These CPU limits are parameters 26 and 25 in section 10.14 of the M68000 User's Manual.

Byte writes

Byte masking uses CAS only. W_n remains common to both lanes, and a part whose CAS stays high does not write.

Write acknowledgement and cycle close

The nominal 150 ns boundary is the earliest WRITE_READY state. It gives CAS one nominal 50 ns active interval before acknowledgement is eligible, exceeding the 18 ns tCAS, 15 ns tWCH, and 15 ns tDH minima before state-output and board delays are subtracted. WRITE_READY raises ACK_ARM; the acknowledgement register samples it on the following 20 MHz rising edge. If the completed path does not retain the DRAM margins and the MC68EC000's 5 ns asynchronous-input setup, delay ACK_ARM by another state.

After acknowledgement, hold the write controls through phase 6. On the next edge, return CAS, RAS, and W high and select row mode. Two precharge phases follow. The controller then waits in phase 9 for REQ_SYNC2 to clear while ACK_ARM stays high.

request accepted; row address already selected
    -> assert selected RAS and W_n
    -> wait 1 tick
    -> select column address
    -> wait 1 tick
    -> assert selected CAS lane or lanes
    -> wait 1 tick
    -> set WRITE_READY
    -> register acknowledgement on the next 20 MHz rising edge
    -> hold the DRAM controls for two more ticks
    -> return CAS, RAS, and W_n high at the phase-6 edge
    -> select row-address mode
    -> keep RAS high for 2 ticks
    -> leave phase 9 after a remembered or current REQ_SYNC2 low
    -> return to IDLE_ARMED

The two precharge states provide 100 ns nominal against the 50 ns tRP minimum. The fixed phase-6 close keeps RAS and CAS below 350 ns even if the CPU request later hangs.

14. DRAM_DTACK_n Generation

DRAM_DTACK_n is the DRAM subsystem's active-low bus acknowledgement. It is asserted only after an accepted read or write reaches its ready state, but it is released directly by the raw CPU bus strobes so that negation does not wait for the RAM decode or the request synchronizer. Bank requests, RAS, and CAS do not drive it directly.

Acknowledgement register

One flip-flop in U_DRAM_ACK, an SN74F74N, holds the internal acknowledgement state ACK_ACTIVE. Its true output 1Q carries ACK_ACTIVE into the external qualification gate described below; the complementary output is unused. The flip-flop's asynchronous clear is wired to motherboard RESET_n for reset only. It is not cleared by the end of a normal CPU bus cycle; instead its 1D input is gated so the register clears synchronously one clock edge after the CPU bus strobes negate.

ACK_D = 0:  ACK_ACTIVE = low  after a clock edge
ACK_D = 1:  ACK_ACTIVE = high after a clock edge

ACK_REQUEST = REQ_SYNC2 AND CPU_REQUEST_ENDED_n
ACK_D = ACK_ARM AND AS_ACTIVE AND BYTE_ACTIVE AND ACK_REQUEST

ACK_ARM is a controller-state output. It may rise only after the read-data or write-cycle timing budget has closed, and it remains high until the accepted request ends. Registering it prevents combinational state-decode glitches from reaching the motherboard acknowledgement tree. Gating 1D with AS_ACTIVE and BYTE_ACTIVE also makes the register fall on its own: when the CPU strobes negate, ACK_D goes low and the next CPU_CLK_DIV2 (20 MHz) rising edge clears ACK_ACTIVE. The physical DRAM_DTACK_n has already been released by the external qualification gate before that edge, so this synchronous clear only has to settle the internal state before the next bus cycle.

Assertion timing

The read and write timelines measure their state boundaries from the edge that asserts RAS, and W for a write. Their earliest READ_READY or WRITE_READY boundary is 150 ns later. The acknowledgement register samples ACK_ARM on the following 20 MHz rising edge:

0 ns     assert selected RAS; assert W_n for a write
150 ns   earliest READ_READY or WRITE_READY; raise ACK_ARM
200 ns   U_DRAM_ACK samples ACK_D (= ACK_ARM, cycle still active)
          ACK_ACTIVE rises after clock-to-output delay
          DRAM_DTACK_n falls one SN74F10 gate delay later

Request acceptance precedes the 0 ns boundary by the row-address setup state. In the baseline sequence, the register edge is therefore nominally 250 ns after request acceptance, not 200 ns. These are nominal state allocations; the electrical timing proof must include clock tolerance and logic, trace, and load delays.

The SN74F74 data sheet gives maximum clock-to-output delays of 7.8 ns low-to-high and 9.2 ns high-to-low over its specified operating range with the stated test load. On assertion, ACK_ACTIVE (1Q) rises after the 7.8 ns low-to-high maximum, and DRAM_DTACK_n then falls after one SN74F10 high-to-low gate delay of at most 5.3 ns (SN74F10, SDFS039A, tPHL, SN74F10 MAX). Because ACK_D is established from the preceding state, it must also meet the F74's data setup and hold requirements at this edge. See the SN74F74 data sheet, SDFS046A, revised October 1993.

The MC68EC000 treats DTACK as asynchronous. At 10 MHz it requires 5 ns of asynchronous-input setup to the clock edge on which DTACK is recognized. If the complete motherboard path misses that edge, the CPU inserts another wait state. The controller keeps the transaction and acknowledgement active, so missing the first sampling edge is safe. It does not remove the separate requirement that read data meet its 5 ns setup time at the edge that actually completes a read.

Strobe-qualified acknowledgement release

The MC68EC000FN10 requires DRAM_DTACK_n to go inactive no later than 110 ns after AS_n or the data strobes negate (parameter 28, section 10.14 of the M68000 User's Manual). The release path must therefore not depend on the request decode, the two-stage request synchronizer, or any controller-state path. The registered acknowledgement is instead qualified directly by the raw CPU bus strobes so that negation propagates through fast local logic only.

U_DRAM_DTACK_GATE, an SN74F10N triple 3-input NAND (period-correct, 5 V TTL, PDIP), forms the qualification. Two of its gates derive the active-high strobe levels and the third drives the external net:

AS_ACTIVE    = NOT AS_n
BYTE_ACTIVE  = NOT (UDS_n AND LDS_n)

DRAM_DTACK_n = NOT (ACK_ACTIVE AND AS_ACTIVE AND BYTE_ACTIVE)

gate 1: NAND(AS_n,  AS_n,  AS_n)                 -> AS_ACTIVE
gate 2: NAND(UDS_n, LDS_n, LDS_n)                -> BYTE_ACTIVE
gate 3: NAND(ACK_ACTIVE, AS_ACTIVE, BYTE_ACTIVE) -> DRAM_DTACK_n
                                                   -> U_DTACK_A pin 1

While the cycle is active, AS_ACTIVE and BYTE_ACTIVE are high, so gate 3 passes the registered acknowledgement: ACK_ACTIVE low keeps DRAM_DTACK_n high, and ACK_ACTIVE high pulls it low. When the MC68EC000 negates AS_n, or negates both UDS_n and LDS_n, the corresponding gate 1 or gate 2 output falls and gate 3 forces DRAM_DTACK_n high after two SN74F10 gate delays, with no dependence on DRAM_CPU_REQ, the request synchronizer, the RAM decode, or the DRAM sequencer. The release path is two fast F-series gate levels.

Using the SN74F10 data sheet (SDFS039A), the two-level local release path is at most 11.3 ns: the first level (gate 1 or gate 2) is an input rising to a NAND output falling, tPHL = 5.3 ns, and gate 3 is then an input falling to a NAND output rising, tPLH = 6.0 ns. Both are the SN74F10 MIN-to-MAX-column maxima at CL = 50 pF, RL = 500 ohm. The CPU-visible release budget is:

t_release = local SN74F10 qualification (2 gate levels)
          + motherboard DTACK release tree (F21 + F21 + F32)
          + PCB and interconnect delay

requirement: t_release <= 110 ns

The 17.2 ns tree figure is from the Acknowledgement Release Path discussion in Bus Architecture and Address Decoding. Qualifying DRAM_DTACK_n with the raw strobes replaces a normal-cycle path that clears the acknowledgement register through DRAM_CPU_REQ and an SN74F08 into the F74 asynchronous clear. That arrangement adds its device delays into the release direction and has no margin against the 110 ns limit. The 81.5 ns shown as remaining is not a verified allocation: it is what is left after the confirmed device delays, before any board delay is counted. Board-dependent release delay is checked by the assembled-board acceptance measurement in the PCB section. The N-package SN74F10, SN74F21, and SN74F32 are also specified only over 0 C to +70 C; see the FAST-family temperature note on the decoder page if the product must run wider.

Assertion passes through gate 3 only. When ACK_ACTIVE rises during an active cycle, DRAM_DTACK_n falls one SN74F10 high-to-low delay later; add that single delay to the F74 clock-to-output figure in the assertion budget above. Assertion delay may add a CPU wait state and is not on the 110 ns critical path.

Acknowledgement register cleanup

Normal CPU bus-cycle end does not asynchronously clear U_DRAM_ACK. Its 1CLR input is wired to motherboard RESET_n for reset only. A stale active acknowledgement is instead removed synchronously by gating the flip-flop's 1D input:

AS_ACTIVE   = NOT AS_n                 (U_DRAM_DTACK_GATE gate 1)
BYTE_ACTIVE = NOT (UDS_n AND LDS_n)    (U_DRAM_DTACK_GATE gate 2)
ACK_REQUEST = REQ_SYNC2 AND CPU_REQUEST_ENDED_n

ACK_ARM_AS      = ACK_ARM AND AS_ACTIVE
ACK_BYTE_REQUEST = BYTE_ACTIVE AND ACK_REQUEST
ACK_D           = ACK_ARM_AS AND ACK_BYTE_REQUEST

While the accepted cycle is active, AS_ACTIVE, BYTE_ACTIVE, and ACK_REQUEST are high, so ACK_D follows ACK_ARM and the register holds its acknowledged state. When the CPU negates AS_n or both byte strobes, ACK_D goes low and the next CPU_CLK_DIV2 (20 MHz) rising edge clears ACK_ACTIVE. The external SN74F10 qualification has already forced DRAM_DTACK_n high by then, so this synchronous clear is off the 110 ns negation path.

U_DRAM_ACK_D, an SN74F08N, uses all four gates: gate 1 combines ACK_ARM and AS_ACTIVE, gate 2 qualifies the synchronized request with the complementary request-end output, gate 3 combines that result with BYTE_ACTIVE, and gate 4 drives ACK_D. The ACK_ARM path still crosses two AND gates; the synchronized request and request-end paths cross three.

The controller testbench exposed a stale-acknowledgement failure with the former three-input ACK_D equation at a 105 ns strobe gap: raw strobes could reassert before ACK_ARM had cleared through the synchronizer. ACK_REQUEST blocks that old state immediately when REQ_SYNC2 is low, and CPU_REQUEST_ENDED keeps it blocked through precharge. The spare third mode flip-flop remembers the low request so phase 9 cannot miss it. No raw bus strobe drives an asynchronous register clear. The regression covers both the stale ACK and the subsequent re-arm failure.

Raw AS_n, UDS_n, and LDS_n now fan out to U_DRAM_DTACK_GATE in addition to their existing motherboard and controller loads. Each SN74F10 input draws at most 0.6 mA in the LOW state (SN74F10, SDFS039A, IIL). Gate 1 ties all three of its inputs to AS_n, so AS_n gains 1.8 mA of FAST IIL; gate 2 puts one input on UDS_n (0.6 mA) and two on LDS_n (1.2 mA). The MC68EC000FN10 guarantees its bus-control outputs to 5.3 mA sink at VOL = 0.5 V, so each strobe still has headroom, but the added current must be carried in the final strobe loading budget with the other motherboard receivers. The F08 limits and PDIP package are in the SN74F08 data sheet, SDFS038A, revised October 1993; the SN74F10 is SDFS039A, revised October 1993.

Motherboard connection

DRAM_DTACK_n is the push-pull TTL output of gate 3 of the U_DRAM_DTACK_GATE SN74F10N. Connect it only to the defined U_DTACK_A input in the motherboard DTACK combining tree; do not wire-OR it with another output. Assertion delay through that tree may add a CPU wait state. The raw strobe inputs to that gate release DRAM_DTACK_n promptly, while the synchronized request-end path later closes CAS and RAS and begins precharge.

15. Timing Limits

These are TMS44400DJ-70 limits, not proposed controller delays. Board logic, buffers, trace delay, and the MC68EC000's data setup requirement must be added before choosing the DRAM_DTACK_n edge. Source: TMS44400 data sheet, pages 8-10.

16. Refresh Requirements

The TMS44400 is dynamic memory. Each part has 1,024 refresh rows, corresponding to address inputs A0..A9, and every row must be refreshed within 16 ms. Normal reads and writes refresh the selected row, but software may repeatedly access only a small part of memory. Dedicated hardware refresh is therefore mandatory.

rows per part                 = 1024
maximum complete interval    = 16 ms
average limit per row        = 16 ms / 1024
                             = 15.625 us

Selected refresh method

The data sheet supports RAS-only, CAS-before-RAS (CBR), and hidden refresh. This controller uses CBR because each TMS44400 supplies its own refresh-row counter; no external refresh address counter or hidden-read sequence is needed.

Each refresh operation drives both shared CAS signals low and then asserts both bank RAS signals. All eight parts receive the same CBR command and each advances its internal counter once. External address inputs are ignored during CBR, so DRAM_ADDR_COL remains low in its defined row-mode state.

CAS_U_n = low
CAS_L_n = low
    then
RAS0_n  = low
RAS1_n  = low

W_n     = high
OE_n    = high

A CBR command with W low puts the TMS44400 into test mode (the WCBR entry cycle). The controller therefore holds W and OE high for the entire refresh operation and never overlaps refresh with a CPU access.

Verified TMS44400DJ-70 limits

These values come from pages 8-10 of the TMS44400 data sheet. The refresh modes, 1,024-cycle interval, test-mode warning, and initialization sequence appear on pages 1, 3, and 4.

CBR state sequence

The following conservative sequence uses the 50 ns nominal CPU_CLK_DIV2 period. Each transition occurs at a rising clock edge. Actual pin intervals must still be checked after state- decode propagation, clock tolerance, loading, and trace delay are known.

This allocation also places successive RAS falling edges at least 200 ns apart, exceeding the 130 ns tRC minimum. It keeps RAS and CAS far below their 10 us maximum low times.

Refresh scheduling and arbitration

Rising edges of U_REFRESH_DIV output Q7 occur every 128 CPU_CLK_10 periods: 12.8 us nominal. Without arbitration delays, 1,024 refreshes take 13.1072 ms, leaving 2.8928 ms before the 16 ms limit. Normal CPU accesses may contribute additional refreshes, but the scheduler does not count them.

A refresh due during a CPU transaction remains pending. The controller completes that transaction, services refresh before accepting another request, and then resumes CPU arbitration. The scheduler must preserve its 12.8 us deadline cadence instead of restarting the timer after a delayed refresh; otherwise repeated CPU delays could consume the 2.8928 ms sweep margin. If more than one deadline can pass while refresh is blocked, the implementation must count the missed services rather than collapse them into one pending bit.

refresh becomes due during CPU access
    -> retain pending refresh
    -> finish the accepted CPU transaction
    -> block the next CPU_START
    -> execute one CBR sequence
    -> service any accumulated refresh credit
    -> return arbitration to the CPU

Final timing closure must prove that the interval between two CBR commands to the same internal row never exceeds 16 ms. That proof must include clock tolerance, the longest legal CPU transaction, refresh state time, and any accumulated service delay.

Power-up and reset initialization

After VCC reaches its full operating level, the TMS44400 requires at least 200 us of pause followed by at least eight initialization cycles, including at least one RAS-only or CBR refresh. This controller uses eight CBR cycles, so initialization uses the same verified waveform as normal refresh.

U_STARTUP_DIV output Q12 provides the startup delay. Its first rising edge follows 2,048 falling edges of CPU_CLK_10, or 204.8 us nominal. At the oscillator's tolerance-only maximum CPU clock of 10.001 MHz, this interval is about 204.78 us and still exceeds the requirement. U_INIT_SYNC synchronizes Q12 before producing INIT_DELAY_DONE. The reset design must also prove that counter release cannot precede the full-VCC reference. See Clock and Reset for the oscillator tolerance and reset timing.

motherboard reset asserted:
    RAS0_n, RAS1_n, CAS_U_n, CAS_L_n = high
    W_n, OE_n, DRAM_DTACK_n           = high

motherboard reset released:
    wait for synchronized U_STARTUP_DIV Q12 high
    execute 8 CBR refresh cycles
    release U_REFRESH_DIV from reset
    enter IDLE_ARMED

Repeating this sequence after a warm motherboard reset is harmless and avoids relying on RAM retention during an arbitrarily long reset. RAM contents after power-up or motherboard reset remain undefined. Reset behavior covers the INIT_WAIT state, the U_DRAM_INIT_CNT cycle counter, and the DRAM_INIT_DONE gate.

17. Refresh Architecture

Two CD74HCT4040E counters separate startup timing from periodic refresh. U_STARTUP_DIV begins when RESET_n rises. U_REFRESH_DIV is held reset until DRAM_INIT_DONE rises, so initialization cannot leave a stale refresh event.

DRAM_CLK_10 falling edges
    -> U_STARTUP_DIV Q12: INIT_DELAY_RAW after 2048 clocks
    -> U_REFRESH_DIV Q7:  REFRESH_EVENT_RAW every 128 clocks

STARTUP_COUNTER_RESET = NOT RESET_n
REFRESH_COUNTER_RESET = NOT (RESET_n AND DRAM_INIT_DONE)

The 4040 advances on each falling CP edge and resets to zero when MR is high. Its Q7 and Q12 pin assignments, negative-edge count, and 10 pF maximum input capacitance are documented in the CD74HCT4040 data sheet. U_DRAM_INV_C generates STARTUP_COUNTER_RESET. Gate 2 of U_DRAM_NAND generates REFRESH_COUNTER_RESET.

U_INIT_SYNC uses the same pin pattern as U_DRAM_REQ_SYNC: Q12 enters pin 2, pin 5 feeds pin 12, and pin 9 is INIT_DELAY_DONE. Pins 3 and 11 use DRAM_CLK_D; pins 1 and 13 use RESET_n; pins 4 and 10 are high; pins 6 and 8 are open; pins 7 and 14 are ground and +5 V.

Q7 is a square wave, not a one-clock pulse. Its first rising edge after initialization occurs after 64 CPU clocks; later rising edges are 128 clocks, or 12.8 us nominal, apart. Only a synchronized Q7 rising edge creates a refresh event. The Q7 level must not directly start or hold the CBR sequencer.

Clock-domain crossing and pending request

Both counter outputs are asynchronous to the 20 MHz controller. U_INIT_SYNC synchronizes Q12. The first three flip-flops in U_REFRESH_SYNC synchronize Q7 and detect its rising edge. Each detected edge increments U_REFRESH_CREDIT, and each normal refresh grant decrements it.

REFRESH_EVENT_RAW
    -> synchronizer and rising-edge detector
    -> add one refresh credit
    -> refresh arbiter
    -> CBR sequencer
    -> remove one credit when complete

The four-bit counter holds as many as 15 credits. The 51.2 us motherboard timeout can span at most five 12.8 us event boundaries after synchronization, so the counter cannot overflow under the stated fault model. Refresh has priority at each idle boundary and drains all stored credits before another CPU start.

CBR control path

A granted refresh uses the CBR waveform in the preceding section. It asserts both byte-lane CAS signals before both bank RAS signals, keeps W_n and OE_n high, leaves the address mux in row mode, and never asserts DRAM_DTACK_n. During a normal CPU access, simultaneous assertion of both bank RAS signals remains forbidden.

Both counters load DRAM_CLK_10, not the motherboard clock directly. Counter propagation delay can move the request time but cannot shorten a CBR pulse because the synchronized event only changes the credit count.

18. Refresh Arbitration

CPU accesses and CBR refresh share the same DRAM controls. Arbitration is non-preemptive: an operation that has asserted a DRAM strobe runs through control release and RAS precharge before another row cycle may start.

Q7 synchronization and event detection

U_REFRESH_SYNC, an SN74F175N, synchronizes the Q7 timer output and detects its rising edge. All four flip-flops use DRAM_CLK_C and share the active-low motherboard reset.

REFRESH_TICK = RT_SYNC2 AND RT_OLD_n

The complementary third-stage output supplies the inversion needed by the edge detector. REFRESH_TICK is high for one 20 MHz interval after a synchronized Q7 rising edge. The refresh-credit counter samples that pulse on the following rising edge.

The SN74F175 requires 3 ns of data setup, 1 ns of data hold, and 5 ns of clear recovery, and its clock-to-output delay is at most 9.5 ns over the specified commercial range. The positive-edge operation, common clear, PDIP ordering code, and limits are documented in the local SN74F175 data sheet, SDFS058B.

Q12 startup synchronization uses the separately assigned U_INIT_SYNC. Flip-flop 4 in U_REFRESH_SYNC is deliberately grounded and unused.

Persistent refresh-credit counter

REFRESH_SERVICE is a one-cycle pulse produced when an idle controller grants one stored refresh credit. Fairchild 74F191PC U_REFRESH_CREDIT counts up for an event, down for a service, and holds when both occur together.

CREDIT_CHANGE = REFRESH_TICK XOR REFRESH_SERVICE
CREDIT_CE_n = NOT CREDIT_CHANGE
CREDIT_UP_DOWN = REFRESH_SERVICE

REFRESH_TICK  SERVICE  action
low           low      hold
high          low      count up
low           high     count down
high          high     hold: one credit arrives as one is consumed

REFRESH_PENDING = CREDIT_Q0 OR CREDIT_Q1 OR CREDIT_Q2 OR CREDIT_Q3

On U_REFRESH_CREDIT, pins 15, 1, 10, and 9 are grounded parallel inputs P0 through P3. Pin 11, active-low parallel load, uses RESET_n, so reset asynchronously loads zero. Pin 4 receives CREDIT_CE_n, pin 5 receives CREDIT_UP_DOWN, and pin 14 receives DRAM_CLK_C. Count outputs Q0 through Q3 are pins 3, 2, 6, and 7. Leave terminal-count pin 12 and ripple-clock pin 13 open. Pins 8 and 16 are ground and +5 V.

The 1980 Fairchild limits require 10 ns count-enable setup and 0 ns hold, and give 9 ns maximum clock-to-Q at 50 pF. The XOR, inverter, and service-decode path has a full preceding clock interval to settle. The counter can hold fifteen credits, while the stated maximum block can accumulate no more than five.

Grant point and priority

DRAM_CAN_START =
    state is IDLE_ARMED
    AND previous RAS precharge is complete
    AND DRAM_INIT_DONE

VALID_CPU_REQUEST =
    REQ_SYNC2
    AND exactly one of RAM0_REQ_n and RAM1_REQ_n is low

REFRESH_SERVICE = DRAM_CAN_START AND REFRESH_PENDING

CPU_START =
    DRAM_CAN_START
    AND NOT REFRESH_PENDING
    AND VALID_CPU_REQUEST

A pending refresh therefore wins at the first legal boundary after the current operation. It never changes RAS, CAS, W, OE, the address mux, or DRAM_DTACK_n in the middle of a CPU access. Continuous CPU traffic cannot pass this boundary and starve refresh.

A CPU request arriving during refresh remains asserted because the MC68EC000 has not received DTACK. The two-stage request synchronizer presents it to the arbiter, and the controller grants it after the CBR sequence and precharge complete. No CPU-request queue is required; there is no other bus master in the baseline system.

Arbitration uses the registered credit count, not the combinational REFRESH_TICK pulse. If a tick is detected on the edge that accepts an otherwise eligible CPU request, that CPU access may start. The newly stored refresh then wins at the next legal boundary. This bounds the added refresh delay to one already accepted CPU operation.

Status

The priority policy, four-bit credit store, Q7 synchronizer, Q12 synchronizer, and grant equations are frozen. The maximum 51.2 us CPU block can add at most five credits, below the counter's capacity of fifteen. Once the CPU cycle ends, six-state CBR operations drain the backlog before another CPU request can start.

19. Reset Behavior

The DRAM controller is in the motherboard reset domain, and RESET_n resets it. The processor's bidirectional reset pin is a separate net, so a CPU RESET instruction does not reset the controller and does not disturb periodic refresh. See Clock and Reset for the reset domains.

Controller state while RESET_n is asserted

While RESET_n is low, the controller holds every DRAM control output at its inactive level.

The request synchronizers, transaction qualifier register, acknowledgement register, refresh-credit counter, both divider counters, mode state, and initialization counter are all forced to their inactive values. Reset must dominate the controller-state decode. The SN74F175 complementary outputs and the enabled CD74ACT244E then hold every active-low DRAM strobe high.

Reset during an active transaction

Motherboard reset may abort a DRAM transaction in progress. The controller does not finish the current read, write, or refresh before entering reset; it returns the DRAM control outputs to their inactive levels at once. A memory location being written at the instant of reset is not guaranteed to hold a defined value afterward. RAM contents are not part of the motherboard-reset architectural state, so this is within spec.

Refresh and retention during reset

Periodic refresh stops while RESET_n is low: both RAS outputs and both CAS outputs stay high, the refresh sequencer is held idle, and the refresh-period counter U_REFRESH_DIV is held cleared. A reset longer than the TMS44400's 16 ms retention interval loses RAM contents. The controller does not clear the array, but software must treat DRAM as undefined after any motherboard reset or power-up.

CPU RESET instruction

A CPU RESET instruction may assert CPU_RESET_n while RESET_n stays inactive. The DRAM controller keeps running, periodic refresh continues, the initialization sequence does not restart, and DRAM contents stay valid. Software-issued RESET instructions do not affect RAM.

Power-up initial pause

After RESET_n is released, the controller enters INIT_WAIT and blocks CPU DRAM transactions until the TMS44400 power-up requirement is met: a 200 us minimum pause followed by at least eight initialization cycles that include at least one refresh (page 4 of the TMS44400 data sheet).

The pause is timed by U_STARTUP_DIV output Q12. Its counter is held cleared during reset and counts CPU_CLK_10 after release. The first Q12 rising edge is 2,048 clocks, 204.8 us nominal, which clears the 200 us minimum with margin. The startup controller leaves INIT_WAIT on the synchronized Q12 edge (INIT_DELAY_DONE) and ignores later Q12 edges until the next reset. See Power-up and reset initialization for the oscillator-tolerance case and the Q12 synchronizer.

Initialization CBR cycles and counter

After INIT_DELAY_DONE, the controller runs eight back-to-back CAS-before-RAS cycles using the same all-device waveform as normal refresh: both CAS outputs low, then both RAS outputs low, with W_n and OE_n high and the address mux in row mode. Every cycle reaches all eight TMS44400 parts, so the sequence contains the required refresh. At the nominal 250 ns CBR occupancy from Refresh requirements, eight cycles take about 2 us, after the 200 us pause rather than instead of it.

U_DRAM_INIT_CNT, an SN74F161AN synchronous 4-bit binary counter, tallies completed startup CBR cycles. It is cleared by RESET_n on its active-low clear input, clocked by DRAM_CLK_C, and count-enabled for one step only when a startup CBR cycle completes.

count 0
    -> CBR 1..8 complete, one count each
    -> INIT_CBR_COUNT = 8  (Q3 output high)
    -> DRAM_INIT_DONE = 1
    -> count enable removed; counter holds at 8

On U_DRAM_INIT_CNT, pin 1 is RESET_n, pin 2 is DRAM_CLK_C, and parallel inputs pins 3 through 6 are grounded. Tie active-low load pin 9 high. Pins 7 and 10 both receive INIT_CBR_DONE. Pins 14, 13, 12, and 11 are INIT_COUNT_QA through INIT_COUNT_QD; pin 11 also supplies DRAM_INIT_DONE. Leave pin 15 open. Pins 8 and 16 are ground and +5 V. The local SN74F161A data sheet documents the SN74F161AN PDIP and its timing.

CPU access during initialization

CPU DRAM transactions are gated by DRAM_INIT_DONE. It is the initialization term in DRAM_CAN_START, the arbitration start condition in Grant point and priority:

DRAM_CAN_START =
    state is IDLE_ARMED
    AND previous RAS precharge is complete
    AND DRAM_INIT_DONE

A DRAM access before DRAM_INIT_DONE is never acknowledged, so the motherboard bus timeout would end it with BERR_n. Boot firmware must run entirely from ROM, including its stack, until the initialization interval has elapsed. Because the initialization timer and the CPU clock come from the same divider tree, firmware can use a conservative CPU-cycle count for that delay instead of an independent wall-clock measurement.

Transition to normal operation

When INIT_CBR_COUNT reaches eight, DRAM_INIT_DONE rises, releases U_REFRESH_DIV from reset, and enables normal CPU arbitration, periodic refresh, and DRAM_DTACK_n generation, then enters IDLE_ARMED. Starting the refresh divider from zero after initialization prevents stale timer events. CBR refresh uses the TMS44400 internal row counters, so no external row-address initialization is needed.

Reset-state summary

Frozen reset architecture

DRAM-controller reset source    : RESET_n
CPU RESET instruction           : does not reset the DRAM controller
Refresh while RESET_n asserted   : disabled
RAM retention across RESET_n     : not guaranteed
Power-up initial pause           : U_STARTUP_DIV Q12 first edge,
                                  2048 CPU_CLK_10 cycles, 204.8 us nominal
Power-up initialization          : 8 consecutive all-device CBR cycles
Initialization cycle counter     : U_DRAM_INIT_CNT, SN74F161AN
Normal RAM access enabled when   : DRAM_INIT_DONE = 1

20. Timing Verification

This section audits the timing of the DRAM controller as already documented on this page. Each path uses the selected parts' maximum delays. Board-dependent delay and skew have explicit acceptance limits to measure on the assembled board.

Method and sources

• MC68EC000FN10 values are the 10 MHz column of the MC68EC000-specific table, M68000UM section 10.14 (M68000 User's Manual). The general M68000 read/write table (section 10.10), which excludes the MC68EC000, is not used.
• TMS44400 values are the -70 column of the TMS44400 data sheet (SMHS562C) timing-requirements and switching-characteristics tables, pages 8-10. The 16 ms tREF is the 5 V TMS44400 figure, not the 128 ms TMS44400P figure.
• Logic-part delays are the exact data-sheet maxima listed in section 20.12. FAST parts use their SN74F (commercial, 0 C to +70 C) MAX columns.
• Clock periods use the C-grade tolerance-only bounds from Clock and Reset; see section 20.11. Minimum-timing checks use the shortest period, never the 50 ns nominal.
• A direct registered control path is one SN74F175N clock-to-Q delay plus one CD74ACT244E data-to-output delay: 9.5 + 9.6 = 19.1 ns maximum at the published loads. The OE assertion path adds one SN74F00N level and is 24.4 ns maximum. Physical delay and skew are verified against the stated limits on the assembled board.
• Local DRAM_DTACK_n is qualified directly by raw AS_n, UDS_n, LDS_n through U_DRAM_DTACK_GATE (SN74F10N), and the F74 1CLR is tied to RESET_n only. No asynchronous-clear release path appears in any timing path below.

Symbols used below
Tdiv2_min = 49.995 ns   shortest CPU_CLK_DIV2 period (one sequencer tick)
Tdiv2_max = 50.005 ns
T10_min   = 99.990 ns   shortest CPU_CLK_10 period
t_ctl     = 19.1 ns max, SN74F175N CLK->Q plus CD74ACT244E data->output
t_oe      = 24.4 ns max, SN74F175N CLK->Q plus SN74F00N plus CD74ACT244E
t_pcb     = measured assembled-board interconnect and loading delay
t_skew    = measured assembled-board control-output skew

Verified MC68EC000FN10 values (section 10.14, 10 MHz)

Note 1 of the table permits subtracting 5 ns from the maximum columns for loads at or below 50 pF; this audit keeps the full published maxima. Note 5: with DTACK meeting #47, the DTACK-to-data setup (#31) is not separately required and read data need only meet #27 on the following clock.

Verified TMS44400-70 values

Access times (max): tRAC 70, tCAC 18, tAA 35, tOEA 18, tOEZ 18. Cycle/pulse (min unless noted): tRC 130, tRAS 70 min / 10,000 max, tCAS 18 min / 10,000 max, tRP 50, tCP 10, tWP 10. Setup/hold: tASR 0, tASC 0, tRAH 10, tCAH 15, tDS 0, tDH 15, tDHR 55, tWCS 0, tWCH 15, tWCR 55, tCWL 18, tRWL 18. CBR: tCSR 5, tCHR 10, tRSH 18, tWSR 10, tWHR 10, tCSH 70. Access-time conditions (not legal maxima): tRCD 20 min / 52, tRAD 15 min / 35. tREF 16 ms (1024 rows). All in ns unless stated. Access times are specified into the data sheet's 100 pF output load circuit.

20.1. Row-address setup path

CPU A1..A10 valid --> 74ACT157 (row selected) --> DRAM A0..A9 --> selected /RAS falls

Setup, tASR (spec 0 ns min):
  The mux data inputs (CPU A1..A10) and the select (DRAM_ADDR_COL low) are both
  stable no later than the CPU_START edge. The read timeline then reserves one
  full state before /RAS falls.
    tASR_actual  >=  Tdiv2_min  -  t_mux(A->Y)  +  t_ctl(/RAS down)  -  t_pcb_skew
                 >=  49.995     -  9.5          +  t_ctl             -  t_pcb_skew
                 =   40.5 ns  +  t_ctl  -  t_pcb_skew          (t_ctl >= 0)
  Requirement 0 ns is met for any t_pcb_skew < 40.5 ns.

Hold, tRAH (spec 10 ns min):
  Row held until DRAM_ADDR_COL rises one tick later; conservatively take no
  credit for the mux select delay.
    tRAH_actual  >=  Tdiv2_min  -  t_skew  -  t_pcb_skew
                 >=  49.995     -  t_skew  -  t_pcb_skew
  Requirement 10 ns is met for any (t_skew + t_pcb_skew) < 39.995 ns.

tASR = 0 ns is not treated as automatically satisfied: the mux A-to-Y delay (9.5 ns) is subtracted explicitly, and the result still shows a 40.5 ns cushion because the CPU row address and the mux select are stable a full state before /RAS. The setup direction does not depend on t_ctl (the row address is stable long before any sequencer output moves); the hold direction needs only bounded sequencer/board skew. Status: PASS. On the assembled board, confirm the address-to-RAS setup and hold at the farthest DRAM.

20.2. Row-to-column transition

DRAM_ADDR_COL rises --> 74ACT157 select --> CPU A11..A20 valid at DRAM A0..A9 --> selected /CAS falls
edges:  /RAS down = tick N ;  column select = tick N+1 ;  /CAS down = tick N+2

Setup, tASC (spec 0 ns min):
    tASC_actual  >=  Tdiv2_min  -  t_mux(select A/B -> Y)  -  t_skew  -  t_pcb_skew
                 >=  49.995     -  14.5                    -  t_skew  -  t_pcb_skew
                 =   35.5 ns  -  t_skew  -  t_pcb_skew
  Requirement 0 ns is met for any (t_skew + t_pcb_skew) < 35.5 ns.

Hold, tCAH (spec 15 ns min):
  Mux stays in column mode from tick N+1 until the cycle closes (returns to row
  mode only when RAS and CAS go high), i.e. many ticks.
    tCAH_actual  >=  several x Tdiv2_min  -  skew   ->  hundreds of ns   PASS

Delay conditions (access-time only, not legal maxima):
    tRCD_actual  =  2 x Tdiv2_min + (t_ctl(/CAS) - t_ctl(/RAS))  >=  99.99 ns - t_skew
    tRAD_actual  =  1 x Tdiv2_min + (t_ctl(col)  - t_ctl(/RAS))  >=  49.995 ns - t_skew
  Both exceed the 52 ns / 35 ns access-time conditions by design, so tRAC (70 ns
  from RAS) does not establish data validity; read completion uses tAA/tCAC/tOEA
  (section 20.3). Both exceed the 20 ns / 15 ns minima with > 30 ns cushion.

The maximum tRAD and tRCD values are access-time limits, and the controller deliberately runs past them with conservative 50 ns state intervals. Status: PASS for setup, hold, and the tRAD/tRCD minima. On the assembled board, verify total column-to-CAS skew remains below the 35 ns cushion.

20.3. Read-data timing

Nominal state boundaries (min-period ticks from /RAS down at tick N):
  tick N   (  0 ns nom):  /RAS low
  tick N+1 ( 50 ns nom):  column select
  tick N+2 (100 ns nom):  /CAS + /OE low
  tick N+3 (150 ns nom):  earliest READ_READY  (architectural boundary only)

Path a  (column address -> tAA -> data at CPU):
  data valid at CPU, relative to tick N+3
    = -2 x Tdiv2_min + t_ctl(col) + t_mux(sel 14.5) + tAA(35) + t_pcb(addr+DQ)
    = -99.99 + t_ctl(col) + 49.5 + t_pcb
    = -50.5 ns + t_ctl(col) + t_pcb

Path b  (/CAS + /OE -> tCAC / tOEA -> data at CPU):
  data valid at CPU, relative to tick N+3
    = -1 x Tdiv2_min + t_ctl(/CAS or /OE) + max(tCAC,tOEA)=18 + t_pcb
    = -49.995 + t_ctl + 18 + t_pcb
    = -32.0 ns + t_ctl + t_pcb

Acknowledgement reaching the CPU /DTACK pin, referenced to tick N+3
  (conservative: U_DRAM_ACK actually samples ACK_ARM one tick later, at N+4,
   which only increases the lead below; assertion transitions are
   F74 CLK->Q up 7.8; F10 g3 down 5.3; F21 down 5.5; F21 down 5.5; F32 down 6.3):
    >= t_F74(7.8) + t_F10(5.3) + t_F21(5.5) + t_F21(5.5) + t_F32(6.3) + t_pcb
    =  +30.4 ns + t_pcb

Data leads DTACK-at-CPU by at least:
    path a:  30.4 - (-50.5) = 80.9 ns  - (t_ctl and t_pcb differences)
    path b:  30.4 - (-32.0) = 62.4 ns  - (t_ctl and t_pcb differences)
Plus the CPU still needs data only 5 ns (#27) before its next latching clock edge.

The 150 ns READ_READY boundary alone does not guarantee valid data; it is the earliest architectural ready state. Final acknowledgement is permitted only because the complete worst-case budget closes: read data reaches the CPU pins 62-81 ns ahead of the acknowledgement edge before the unquantified terms, and the CPU data-in setup is only 5 ns. DRAM output loading: each DQ drives one MC68EC000 data input (Cin 20 pF, M68000UM 10.13) plus the other bank's DQ pin and the motherboard-wide data-bus load. No access-time derating is needed if the assembled-board measurement is at most 100 pF per bit and the data lead at the CPU is at least 5 ns. The direct control delay is 19.1 ns and the OE delay is 24.4 ns, so the slower control path leaves 38.0 ns of the original 62.4 ns lead before board delay. Status: PASS by design; verify the 100 pF load and 5 ns CPU-pin setup on the assembled board.

20.4. Read acknowledgement timing

READ_READY / ACK_ARM --> U_DRAM_ACK_D (2x SN74F08) --> U_DRAM_ACK 1D
  --> U_DRAM_ACK (SN74F74) 1Q = ACK_ACTIVE --> U_DRAM_DTACK_GATE g3 (SN74F10)
  --> U_DTACK_A (SN74F21) --> U_DTACK_B (SN74F21) --> U_OR_DTACK (SN74F32) --> CPU /DTACK

D-input setup at U_DRAM_ACK (ACK_ARM is a registered state output; AS_ACTIVE and
BYTE_ACTIVE and ACK_REQUEST are already high during an accepted cycle):
    setup_slack = Tdiv2_min - tCQ(F175 8.5) - 2 x tPHL(F08 6.6)
                  - tsu(F74 D, 3) - t_pcb - t_clock_skew
                = 49.995 - 8.5 - 13.2 - 3 - t_pcb - t_clock_skew
                = 25.3 ns - t_pcb - t_clock_skew
    request-qualification paths cross three F08 gates:
        conservative slack = 49.995 - 9.2 - 19.8 - 3 - t_pcb - t_clock_skew
                           = 18.0 ns - t_pcb - t_clock_skew
    Verify setup and hold on all four ACK_D gates and the new mode-bit path;
    Icarus does not enforce the device models' specify timing checks.

Assertion delay from the U_DRAM_ACK clock edge to CPU /DTACK low:
    t_assert = tPLH(F74 CLK->Q, 7.8)   [1Q = ACK_ACTIVE rises]
             + tPHL(F10 gate 3, 5.3)   [DRAM_DTACK_n falls]
             + tPHL(F21 L1, 5.5) + tPHL(F21 L2, 5.5)
             + tPHL(F32, 6.3)          [DTACK_n falls]
             + t_pcb(DTACK net)
           = 30.4 ns + t_pcb        (local F10 = 5.3, global tree = 17.3)

MC68EC000 #47 asynchronous input setup = 5 ns min. If DTACK settles later than
5 ns before a CPU sampling edge, recognition slips to the next edge: the
controller holds ACK_ACTIVE and every strobe, so the CPU simply inserts one
more wait state. No transaction is lost.

The revised ACK_ARM setup budget is 25.3 ns before board delay and clock skew; the added request-qualification paths have a conservative 18.0 ns budget. The output assertion path remains 30.4 ns before board delay. The controller regression passes with modeled propagation delays; setup, hold, fanout, and clock skew still require schematic and board verification. The registered ACK_ARM output settles one full clock before the acknowledgement register samples it. Measure at least 3 ns of setup at U_DRAM_ACK and 5 ns at the CPU pin.

20.5. /DTACK release timing

/AS negated  (or both /UDS and /LDS negated)
  --> U_DRAM_DTACK_GATE (SN74F10N) local qualification
        g1: NAND(AS_n,AS_n,AS_n) -> AS_ACTIVE          input rises, output falls:  tPHL(F10) = 5.3
        g3: NAND(ACK_ACTIVE,AS_ACTIVE,BYTE_ACTIVE)     input falls, output rises:  tPLH(F10) = 6.0
        (byte-strobe route is g2 tPHL 5.3 then g3 tPLH 6.0, identical total)
      local release  = 5.3 + 6.0 = 11.3 ns
  --> U_DTACK_A  (SN74F21)  DRAM_DTACK_n rises -> group AND rises:  tPLH(F21) = 5.3
  --> U_DTACK_B  (SN74F21)  final AND rises:                       tPLH(F21) = 5.3
  --> U_OR_DTACK (SN74F32)  DTACK_RAW_n rises -> OR rises:          tPLH(F32) = 6.6
      global tree    = 5.3 + 5.3 + 6.6 = 17.2 ns
  --> CPU /DTACK high

verified logic delay      = 11.3 + 17.2 = 28.5 ns maximum
MC68EC000FN10 #28 limit   = 110 ns
remaining CPU budget      = 110 - 28.5 = 81.5 ns
  for /AS(/DS) receiver threshold-to-gate, PCB trace, connector, and
  DRAM_DTACK_n / DTACK_n net loading

Assembled-board acceptance: /AS(/DS) receiver plus PCB/interconnect plus loaded
      net delay must stay at or below 81.5 ns.

Releasing through the request path instead of the raw strobes (DRAM_CPU_REQ -> SN74F08 -> the F74 asynchronous clear) does not meet this limit. The architecture here qualifies DRAM_DTACK_n with the raw CPU bus strobes through two fast SN74F10 gate levels and does not wait for the synchronized request path; the F74 clear is RESET_n only. Datasheet sources for the numbers above: SN74F10 SDFS039A (tPHL 5.3, tPLH 6.0), SN74F21 SDFS006A (tPLH 5.3), SN74F32 SDFS044B (tPLH 6.6). The N-package FAST parts are specified only over 0 C to +70 C. Status: logic PASS. Accept the assembled board only if the measured CPU-pin release is at most 110 ns; the physical portion has an 81.5 ns allowance.

20.6. Write-data timing

MC68EC000 write data valid --> (CPU keeps driving; controller does not latch it)
  --> TMS44400 early-write: W_n low first, so the selected /CAS falling edge is
      the controlling write-data event (tDS/tDH referenced to the later of CAS or W)

CPU delivers (MC68EC000FN10 10 MHz):
  #26 data-out valid to DS asserted (write) = 30 ns min   -> data valid >= 30 ns before /DS
  #25 AS,DS negated to data-out invalid    = 30 ns min    -> data held  >= 30 ns after strobes negate

Controller inserts before /CAS falls: byte-strobe qualification + 2 x CPU_CLK_DIV2
synchronizer stages + CPU_START + 2 sequencer ticks (row, column)  >=  4 x Tdiv2_min
  ~ 200 ns  after /DS asserted.

    tDS_actual  ~  30 ns (#26) + 200 ns (sync + sequencer) - t_ctl(/CAS) + t_pcb(data)
                ~  230 ns                        vs  tDS spec = 0 ns min       PASS
    tDH_actual  :  CPU cannot negate its strobes until it has seen /DTACK, which
                   is after READ/WRITE_READY; /CAS fell ~200 ns into the cycle, so
                   data stays valid for hundreds of ns after /CAS down, and the
                   CPU still holds it 30 ns past strobe negation (#25)
                                                 vs  tDH spec = 15 ns min      PASS
    tWCS  (W low before CAS low, 0 min)  : W down at tick 0, CAS down at tick +2
                   = 2 x Tdiv2_min - t_skew  =  99.99 ns - skew            PASS
    tWCH  (W low after CAS low, 15 min)  : W held low through cycle close       PASS
    tWP   (W low pulse, 10 min)          : W low for the whole DRAM cycle       PASS
    tCWL  (W low before CAS high, 18 min): W low throughout the CAS pulse       PASS
    tRWL  (W low before RAS high, 18 min): W low throughout the RAS pulse       PASS
    tWCR  (W low after RAS low, 55 min)  : W down and RAS down share a state
                   boundary; W then stays low >= 2 x Tdiv2_min to /CAS and past
                   cycle close  =  99.99 ns - t_skew   vs 55 ns
                                                 PASS for t_skew < 44.99 ns
    tDHR  (data hold after RAS low, 55)  : data valid hundreds of ns after RAS  PASS

The DRAM early-write needs data valid 0 ns before the controlling CAS edge (tDS = 0) and held 15 ns after. The controller actually presents data about 230 ns before /CAS falls, because the request must cross two 20 MHz synchronizer stages and two sequencer ticks after the CPU asserts its data strobe, and the data is then held for the entire remaining bus cycle because the CPU cannot release it until /DTACK is seen. The margin is the synchronizer plus sequencer latency, which the architecture guarantees is at least four CPU_CLK_DIV2 ticks. Status: PASS. The direct registered RAS and W paths use matched CD74ACT244E channels. Their measured pin-to-pin skew must remain below 44.99 ns; the tighter RAS pulse check below controls the actual acceptance limit.

20.7. /RAS and /CAS pulse widths

Nominal 50 ns state widths are not relied on directly. The design allocates two ticks wherever a limit equals one nominal state (tRP, tRAS), so the worst-case interval is two minimum periods, 99.99 ns, against the 50-70 ns requirement. The fixed phase-6 close ends the DRAM cycle before the controller waits for request release, so a hung CPU bus cycle cannot extend a DRAM strobe. Status: PASS for minimum and maximum pulse widths.

20.8. Refresh CBR timing

Frozen CBR sequence (offsets = min-period ticks):
  tick 0        : CAS_U_n, CAS_L_n low
  tick +1 ( 50) : RAS0_n, RAS1_n low
  tick +3 (150) : RAS high
  tick +4 (200) : CAS high
  tick +5 (250) : next operation may begin
  W_n, OE_n high throughout; address mux stays in row mode

  tCSR  (CAS low to RAS low, 5 min)   = 1 tick = 49.995 - t_skew - t_pcb_skew   PASS (cushion 44.995)
  tCHR  (RAS low to CAS high, 10 min) = 3 ticks = 149.985 - skew                    PASS
  tRSH  (CAS low to RAS high, 18 min) = 3 ticks = 149.985 - skew                    PASS
  tRAS  (RAS low pulse, 70 min)       = 2 ticks =  99.99  - t_skew(down vs up)  PASS (cushion 29.99)
  tRP   (RAS precharge, 50 min)       = >= 2 ticks to next RAS down =  99.99 - skew  PASS
  tRC   (RAS down to RAS down, 130)   = 4 ticks = 199.98 - skew                     PASS
  tCP   (CAS high, 10 min)            = >= 1 tick between refreshes = 49.995 - skew  PASS
  tWSR / tWHR (W high setup/hold, 10) : W is never asserted during refresh          PASS
  tCAS low (18 min / 10 us max)       = 4 ticks = 199.98 ns  (well under 10 us)      PASS

Status: PASS for every CBR limit. The tightest are tCSR (44.995 ns cushion) and tRAS (29.99 ns cushion). Measure control-output skew on the assembled board and keep it below the acceptance limits in the PCB section.

20.9. Refresh-rate proof

CPU_CLK_10               = 10 MHz nominal   (9.999 - 10.001 MHz, C-grade tolerance-only)
U_REFRESH_DIV            = CD74HCT4040E ripple counter
Q7 rising edge interval  = 128 CPU_CLK_10 periods = 12.8 us nominal
1024 refresh events      = 1024 x 12.8 us = 13.1072 ms   (nominal)
                           1024 x (128 / 9.999 MHz) = 13.1085 ms  (slowest clock)
TMS44400-70 tREF         = 16 ms for all 1024 rows
nominal headroom         = 16 - 13.1072 = 2.8928 ms
slowest-clock headroom   = 16 - 13.1085 = 2.8915 ms

Arbitration is non-preemptive. A CPU transaction that has already asserted a DRAM strobe runs through control release and RAS precharge, but once REFRESH_PENDING is set from a synchronized Q7 rising edge, CPU_START is blocked (CPU_START requires NOT REFRESH_PENDING) and refresh takes the next DRAM_CAN_START grant. Every CPU grant is followed by a mandatory return through IDLE_ARMED, where a pending refresh has strict priority, so continuous CPU traffic cannot pass the grant boundary often enough to starve refresh.

The extra delay a single pending refresh can suffer is at most one non-preemptive transaction: about 0.4 us for a normally completed CPU cycle (RAS low plus two precharge ticks), or at most about 51.2 us if a CPU cycle hangs and is ended by the motherboard bus timeout. Both are far inside the 2.89 ms sweep headroom. The 74F191 stores every deadline crossed during that delay. Five queued CBR cycles take at most 1.5 us, after which the 12.8 us cadence continues. Status: PASS. The 13.1085 ms slow-clock sweep plus 51.2 us blocking and 1.5 us backlog drain is 13.1612 ms, leaving more than 2.83 ms before the 16 ms limit.

20.10. Reset / initialization timing

U_STARTUP_DIV MR = STARTUP_COUNTER_RESET = NOT RESET_n
  -> counter held at 0 while RESET_n low; counts DRAM_CLK_10 after RESET_n high
Q12 first rising edge = 2048 CPU_CLK_10 periods

  nominal            : 2048 / 10.000 MHz         = 204.800 us
  fastest tolerance  : 2048 / 10.001 MHz         = 204.780 us   -> +4.780 us over 200 us
  + first-year aging : 2048 / 10.00105 MHz       = 204.779 us   -> +4.779 us over 200 us
  fails only above   : 2048 / 200 us             =  10.240 MHz  (+2.40 %, 240x C-grade tol)

The 200 us minimum is not proven from nominal frequency alone. Using the C-grade tolerance-only upper bound of 10.001 MHz from Clock and Reset, and again with the +5 ppm first-year aging that page's tolerance policy includes, the first Q12 edge is 204.78 us, still 4.78 us above the requirement. The oscillator would have to be 2.4 % fast to drop below 200 us. The CD74HCT4040 Q12 ripple delay (about 50 ns for the first stage plus 19 ns per stage, under 0.3 us total) is negligible at this scale. Counter release cannot precede full VCC: RESET_n is not released until the Clock and Reset power-on sequence has held reset at least 110 ms after valid supply (10 ms oscillator start plus 100 ms hold), by which time CPU_CLK_10 is at its specified rate. Jitter and TTL-level symmetry are unspecified for the SG-615PH and remain a post-layout measurement item, but random cycle-to-cycle jitter over 2048 periods cannot shift 204.8 us below 200 us.

Eight initialization CBR cycles:
  U_DRAM_INIT_CNT (SN74F161AN, SDFS056B) cleared by RESET_n, clocked by DRAM_CLK_C,
  count-enable one step per completed startup CBR; DRAM_INIT_DONE at count 8.
  CLK->Q <= 9.5 ns, tsu(ENT) <= 9.5 ns vs the 49.995 ns period  -> count logic closes.
  8 CBR cycles x ~250 ns = ~2 us, after the 200 us pause.

CPU RAM access blocked until init done:
  DRAM_CAN_START includes AND DRAM_INIT_DONE ; CPU_START requires DRAM_CAN_START.
  Before DRAM_INIT_DONE there is no CPU_START and no DRAM_DTACK_n, so a premature
  DRAM access is never acknowledged and is ended by the motherboard bus timeout.

Status: PASS - 204.78 us worst-case versus 200 us required (4.78 us margin; failure needs a +2.4 % frequency error). The SN74F161A data sheet (SDFS056B) documents the SN74F161AN PDIP and its FAST limits. Measure startup interval and clock symmetry on the assembled board; accept only an interval of at least 200 us before the first CBR edge.

20.11. Clock tolerance

Source: clock-and-reset.html, SG-615PH C grade, +/-100 ppm frequency tolerance
        (-20 to 70 C), plus <= +/-5 ppm first-year aging; jitter unspecified.

  master 40 MHz  : 39.996  - 40.004  MHz
  CPU_CLK_10     :  9.999  - 10.001  MHz  ->  period 99.990  - 100.010 ns
  CPU_CLK_DIV2   : 19.998  - 20.002  MHz  ->  period 49.9950 -  50.0050 ns

  Including +5 ppm aging (worst-fast): CPU_CLK_DIV2 ~ 49.9948 ns, CPU_CLK_10 ~ 99.9895 ns
  (< 0.3 ppm change; no conclusion in this section changes)

Values used for minimum-timing checks:
  one sequencer tick   Tdiv2_min = 49.995 ns
  two ticks                       99.990 ns
  three ticks                    149.985 ns
  CPU_CLK_10 period    T10_min  =  99.990 ns

Applied to: tRP (2 ticks = 99.99 vs 50), tRAS (2 ticks = 99.99 vs 70),
tCAS min (1 tick = 49.995 vs 18), tCSR (1 tick = 49.995 vs 5),
tCHR (3 ticks = 149.985 vs 10), 200 us startup (2048 x T10_min = 204.78 us vs 200).
A 50 ns nominal tick is never compared directly against a 50 ns minimum; that is
why tRP is allocated two ticks.

20.12. Logic-delay sources

20.13. Final status

The logic design now closes every named timing path. Layout-dependent delay is handled by the assembled-board acceptance measurements below; it is not represented by guessed PCB numbers. The fixed cycle close also keeps a hung CPU request from holding a DRAM strobe past its 10 us limit.

21. Electrical Compatibility and Fanout

All DRAM logic runs from the same 5 V rail. Keep that rail inside the MC68EC000's 4.75 V to 5.25 V range at every device. The address muxes and external strobe driver are ACT parts with TTL input thresholds; the state, decode, and glue logic is FAST TTL. No level shifter is required.

1994 cutoff: PASS. The 1994 Harris Product Selection Guide lists CD54/74AC/ACT157, CD54/74AC/ACT244, and CD54/74HC/HCT4040; suffix E is plastic DIP. TI's 1991 MOS Memory Data Book contains the exact TMS44400-70 and DJ package. The Motorola manual is copyright 1993, the Philips 74F194 specification is dated April 4, 1989, and the Fairchild 1980 FAST data book lists the plastic-DIP 74F191PC. The cited TI FAST parts have 1987 original publication dates. Every selected semiconductor was available by the absolute 1994 cutoff.

Verified data-sheet limits

The supplied TMS44400 table confirms every project value in the task. Its capacitance row is printed as A0-A10, although the installed x4 device exposes the ten address inputs A0..A9. The 7 pF DQ figure is specifically Co, output capacitance. No corrected numerical value is required. The TMS44400's 2.4 V HIGH threshold is used below; treating it as a generic 2.0 V TTL input would overstate HIGH margin by 0.4 V.

HIGH noise margin = VOH(min) - VIH(min)
LOW noise margin  = VIL(max) - VOL(max)

PASS requires both results >= 0 V at the stated output current.

Logic-level compatibility

A direct SN74F output would be compatible with a TMS44400 control input, but only narrowly on the HIGH side: 2.5 V - 2.4 V = 0.10 V HIGH and 0.8 V - 0.5 V = 0.30 V LOW. The selected ACT244 accepts that FAST output and drives the DRAM controls with 1.30 V HIGH margin. ACT, not AC, supplies the needed TTL input thresholds.

U_DRAM_INV_A, an SN74F04N, creates NOT R/W for the Philips N74F194N transaction register. The CPU-to-FAST input margins are 2.00 V HIGH and 0.30 V LOW; the FAST-to-FAST output margins are 0.50 V HIGH and 0.30 V LOW.

Address-mux output loading

one CD74ACT157E DRAM-address output
  -> 8 x TMS44400 address input

known DRAM capacitive load = 8 x 5 pF = 40 pF max
DC input leakage magnitude = 8 x 10 uA = 80 uA max

CD74ACT157E rated drive     = 24 mA source / 24 mA sink
current utilization         = 0.080 mA / 24 mA = 0.33 %

PASS for DC fanout. The 80 uA worst-case receiver current is below either 24 mA output rating, and the address-level margins are 1.30 V HIGH and 0.30 V LOW. The data sheet characterizes both the 14.5 ns select path and the 9.5 ns data path at 50 pF. The known 40 pF DRAM-pin load leaves 10 pF for interconnect and probe. Measure the farthest address output with the board assembled. If the completed load exceeds 50 pF or the measured mux delay exceeds 14.5 ns, use the measured delay in the row and column timing calculations.

CPU address-bus input loading

The frozen mapping connects each CPU line A1..A10 to one row-data input and each line A11..A20 to one column-data input. No CPU address line drives two mux inputs.

per CPU address line A1..A20:
  receiver count            = 1 x CD74ACT157E data input
  DC input leakage          = +/-1 uA max
  input capacitance         = 10 pF max

MC68EC000 address drive:
  HIGH                      = 400 uA source at VOH(min) = 4.00 V
  LOW                       = 3.2 mA sink at VOL(max) = 0.50 V
  published output CL limit = 130 pF

DRAM-mux increment only:
  HIGH current fraction     = 1 uA / 400 uA = 0.25 %
  LOW current fraction      = 1 uA / 3.2 mA = 0.031 %
  capacitance fraction      = 10 pF / 130 pF = 7.7 %

PASS for the mux increment. One CMOS input is not zero load, but its 1 uA and 10 pF maxima are small compared with the CPU guarantees. On the assembled motherboard, verify each CPU address net remains at or below 130 pF and reaches a valid logic level before the request is accepted.

DRAM control-net fanout

The RAS and CAS loads are 28 pF before interconnect. During a normal access, the active CAS lane reaches both banks, but the unselected bank keeps RAS high. This adds the second bank's CAS input current and capacitance without selecting its array or enabling its DQ outputs. It does not create contention.

W_n and OE_n are the heavier control loads: each is already 56 pF before PCB/interconnect capacitance, above the ACT244's 50 pF timing condition. Their 80 uA DC load is far below the driver's 24 mA rating, so this is a delay and edge-quality check, not a fanout failure. Measure both signals at the farthest DRAM and use the observed delays in the write and tOEA/tOEZ checks.

CPU strobe and mixed-family loads

AS_n  -> 3 tied SN74F10N inputs: LOW load = 3 x 0.6 mA = 1.8 mA
UDS_n -> 1 SN74F10N input:       LOW load = 1 x 0.6 mA = 0.6 mA
LDS_n -> 2 tied SN74F10N inputs: LOW load = 2 x 0.6 mA = 1.2 mA

HIGH loads are 3 x 20 uA = 60 uA, 20 uA, and 40 uA respectively.
MC68EC000 bus-control drive is 400 uA source / 5.3 mA sink.

PASS for the added SN74F10N loads. The largest added LOW load is 1.8 mA on AS_n, below the CPU's 5.3 mA sink guarantee. The existing motherboard receivers still belong in the complete strobe budget. Because the SN74F10 sheet gives no input capacitance, accept the completed strobe net only with valid TTL levels, no double crossing, and the timing limits stated above.

CPU_CLK_10 drives the CPU and the four inputs of U_DRAM_CLK_BUF. The buffer outputs, not the motherboard divider, drive both HCT4040 counters and the controller clocks. Verify the source clock and each branch at its farthest receiver; no branch may double-clock or violate its receiver threshold.

U_REFRESH_DIV Q7 drives one SN74F175N input; U_STARTUP_DIV Q12 drives one SN74F74N input. Each HCT output has 1.84 V HIGH and 0.47 V LOW margin and ample current for one FAST receiver. Where the FAST sheet omits input capacitance, confirm a clean single transition at the receiving pin.

Data-bus loading

Each CPU data bit connects to one DQ pin in bank 0 and the corresponding DQ pin in bank 1. One bank may drive during a read; the other bank remains high-impedance but its pin capacitance remains on the net.

per CPU Dn line:
  2 x TMS44400 DQ capacitance = 2 x 7 pF = 14 pF max
  1 x MC68EC000 input         = 20 pF max
  known subtotal              = 34 pF max
  plus other motherboard receivers, PCB/interconnect, sockets, and probe

selected DRAM output drive    = 5 mA source at VOH >= 2.4 V
                                4.2 mA sink at VOL <= 0.4 V
known receiving DC current    = 20 uA CPU input
unknown physical terms        = other motherboard loads, routes, sockets, probe
special condition             = unselected bank has RAS=HIGH, CAS=LOW, OE=LOW

The data-level check passes numerically: 0.40 V HIGH margin and 0.40 V LOW margin from a TMS44400 to the CPU, and 1.60 V HIGH plus 0.30 V LOW from the CPU to the DRAM during writes. The DRAM access times are characterized with a 100 pF output load, so the 34 pF known subtotal leaves 66 pF for every other connected pin and physical term before reaching that condition. The assembled-board test enforces both the 100 pF condition and the CPU's 5 ns data setup directly.

The supplied TMS44400 sheet specifies IO = +/-10 uA with CAS HIGH, not for the shared-CAS condition above. Do not substitute that number. Verify valid CPU HIGH and LOW levels with the other bank deselected, and verify no bus-current or waveform evidence of contention. Keep each completed read net at or below 100 pF.

Local current and power implications

The TMS44400DJ-70 lists ICC1 = 90 mA max per part for a minimum-length read/write cycle and ICC3 = 90 mA max per part for minimum-cycle RAS-only or CBR refresh, both at VCC = 5.5 V and with no output load. Four active parts in one bank therefore contribute up to 4 x 90 mA = 360 mA by that read/write test condition. An all-device CBR operation contributes up to 8 x 90 mA = 720 mA by the refresh-current test condition. These are summed data-sheet maxima, not measured peak currents and not a motherboard power budget.

All-device CBR is the worst local transient. The decoupling network below is arranged around that event; final acceptance requires the rail to remain between 4.75 V and 5.25 V at the farthest DRAM.

Unused inputs

No input may be left floating. Unused push-pull outputs remain open; they are not tied to either rail.

Output contention

• DRAM data bus: PASS for the frozen DRAM protocol. A normal read asserts RAS for one bank only. A write has OE_n HIGH and uses early write, so the CPU is the only driver. CBR refresh keeps OE_n HIGH, so neither bank drives. The unselected bank's DQ capacitance remains present.
• DRAM address bus: PASS. Each net has one CD74ACT157E push-pull output. Enables are tied LOW; no mux outputs are paralleled.
• RAS, CAS, W, and OE: PASS. Each net has one CD74ACT244E output and only DRAM inputs as loads.
• DRAM_DTACK_n: PASS. It is the push-pull output of gate 3 in U_DRAM_DTACK_GATE and drives only the defined U_DTACK_A input. It is not wire-ORed.
• Global DTACK_n tree: PASS. The SN74F21/SN74F32 tree combines logic levels through gate inputs; it does not connect push-pull outputs together.

Before fabrication, run the schematic electrical-rules check and confirm that ROM, I/O, expansion transceivers, CPU writes, and both DRAM banks never enable two push-pull outputs on one data net.

Final load table

Final status

The selected parts pass the DC logic-level and current-fanout checks. Board-dependent values have explicit acceptance limits in the next section.

22. PCB and Decoupling Notes

Placement and routing

• Place the eight DRAMs as two compact four-part banks. Put the three address muxes between the CPU address routes and the DRAM address bus.
• Place U_DRAM_STROBE beside the DRAM banks. Route RAS, CAS, W, and OE as short trees with comparable branch lengths and no long unterminated stubs.
• Place U_DRAM_CLK_BUF beside the controller registers. Route branches A-D separately; do not daisy-chain clocked packages.
• Use an unbroken ground plane under the controller, address muxes, DRAMs, and all clock and control routes. Give each DRAM bank several low-inductance +5 V and ground connections.
• Include an unpopulated series-resistor footprint at the source of each clock branch and each heavily loaded W/OE route. Fit a damping value only if the assembled waveform needs it, then recheck delay.

Decoupling values

• Fit one 0.1 uF X7R ceramic capacitor at every IC and every DRAM, directly between that package's VCC and GND pins.
• Fit one 4.7 uF tantalum or low-ESR electrolytic capacitor per four-DRAM bank, beside the center of the bank.
• Fit one 22 uF electrolytic capacitor at the controller/DRAM power entry and one additional 0.1 uF ceramic beside it.

CBR refresh switches all eight DRAMs and is the supply test case. Probe VCC and ground at the farthest DRAM with a short ground spring. The observed rail must stay between 4.75 V and 5.25 V. If it does not, shorten the current loop or add local bulk capacitance before changing logic timing.

Assembled-board acceptance

Record oscilloscope screenshots and probe locations with the board revision. These measurements close the quantities represented by t_pcb, t_pcb_skew, and loaded output delay in the timing audit.

23. Implementation Checklist

The logic design is complete. Before release, the schematic, layout, and assembled-board record must show:

• three CD74ACT157E address muxes connecting A1..A20 to DRAM A0..A9;
• U_DRAM_REQ_SYNC, U_DRAM_TX, U_DRAM_ACK (with 1CLR to RESET_n only and the gated ACK_D input), U_DRAM_DTACK_GATE (SN74F10N), and U_DRAM_ACK_D (SN74F08N) with the pin connections, reset behavior, and setup checks defined above;
• the F161 phase counter, two F138 decoders, three F175 state/control registers, and the FAST glue packages assigned above;
• U_DRAM_CLK_BUF and U_DRAM_STROBE, both CD74ACT244E, with every unused input grounded;
• write and output-enable paths that meet the -70 timing table at each part;
• a read-data timing budget from RAS, CAS, and column address through the board to the CPU, ending before DRAM_DTACK_n;
• the DRAM_DTACK_n release path: two SN74F10 local gate levels plus the motherboard SN74F21 + SN74F21 + SN74F32 tree, whose device delays total 28.5 ns against the MC68EC000's 110 ns limit (checked against SN74F10 SDFS039A, SN74F21 SDFS006A, and SN74F32 SDFS044B), with the measured loading and PCB delay still to be added and the total shown to stay within 110 ns, and the SN74F 0 C to +70 C range confirmed against the product operating range;
• the 74F191PC refresh-credit counter and proof that a forced 51.2 us transaction accumulates no more than five credits;
• separate U_STARTUP_DIV and U_REFRESH_DIV counters, U_REFRESH_SYNC, the Q12 startup synchronizer, the refresh-priority logic, U_DRAM_INIT_CNT with the eight-CBR count and DRAM_INIT_DONE gate, and the eight CBR initialization cycles; and
• the specified per-package, per-bank, and power-entry capacitors; and
• every measurement in the assembled-board acceptance table, saved with the board revision and probe location.

24. Sources

• Texas Instruments, TMS44400 1048576 by 4-Bit Dynamic Random-Access Memory, SMHS562C. Organization, pinout, DJ package, -70 timing requirements and switching characteristics, refresh modes, and the power-up initialization sequence.
• Motorola, M68000 User's Manual, section 10.13 (DC characteristics and capacitance) and section 10.14 (MC68EC000 10 MHz AC characteristics).
• Texas Instruments FAST logic: SN74F00, SN74F02, SN74F04, SN74F08, SN74F10, SN74F20, SN74F21, SN74F30, SN74F32, SN74F86, SN74F74, SN74F138, SN74F161A, and SN74F175. The exact parameters used appear in section 20.12.
• Texas Instruments, CD74ACT157 (SCHS340D), CD74ACT244 (SCHS287C), and CD74HCT4040 (SCHS203E). Address multiplexers, clock and control buffers, and the startup and refresh counters.
• Philips, 74F194 4-Bit Bidirectional Universal Shift Register, April 1989. The N74F194N transaction register.
• Fairchild, FAST Data Book, 1980. The 74F191PC refresh-credit counter.
• The project Bus and Address Decode supplies RAM0_REQ_n and RAM1_REQ_n and consumes DRAM_DTACK_n; Clock and Reset supplies CPU_CLK_DIV2, CPU_CLK_10, and RESET_n; and Memory Map fixes both bank address ranges.