Floppy Controller

1. Purpose and Scope

The 82077AA-1 controls both installed D359M3D drives. The controller supplies the data separator, write precompensation, drive-control outputs, status logic, and a 16-byte FIFO. The motherboard adds a lower-byte host adapter, a standard twisted drive cable, and two separately fused drive-power outputs.

The Memory Map owns I/O slot 1 and the canonical register addresses. Bus and Address Decode owns IO1_n, the completion tree, and bus-timeout behavior. The MFP owns GPIP5 and vector $47. The Clock and Reset design owns PERIPH_RESET_n, and the MFP clock divider supplies MFP_CLK_5 to the bus-response sequencer.

Signal names ending in _n, and names written with a leading slash, are active low. The logic supply is +5 V. Every IC family selected by this page existed before 1994.

2. Architecture

MC68EC000 lower byte                  Intel 82077AA-1

D7..D0 <--------------------------> DB7..DB0
A3..A1 ----------------------------> A2..A0
IO1_n + LDS_n --> FDC_CYCLE --> FDC_CS_n --> CS
R/W + FDC_CYCLE --> FDC_RD_n ------> RD
R/W + FDC_CYCLE --> FDC_WR_n ------> WR
MFP_CLK_5 --> response sequencer --> FDC_DTACK_n
PERIPH_RESET_n --> inverter -------> RESET
INT --------------------------------> MC68901 GPIP5

24 MHz crystal ---------------------> X1, X2

82077AA-1 drive interface
    |
    +-- output damping resistors
    +-- 34-pin motherboard header
            |
            +-- drive 1 before twist: Mitsumi D359M3D
            |
            +-- cable twist
                    |
                    +-- drive 0 and boot drive: Mitsumi D359M3D

+5 V  -- RXEF110 --> drive 0 mini-Berg pin 1
+12 V -- RXEF050 --> drive 0 mini-Berg pin 4
+5 V  -- RXEF110 --> drive 1 mini-Berg pin 1
+12 V -- RXEF050 --> drive 1 mini-Berg pin 4

The controller runs in PS/2 mode with its internal drive buffers enabled. Both drives retain their factory PC configuration: drive select 1 on cable pin 12 and disk-change on pin 34. The cable twist maps the far drive to controller drive 0 without modifying either drive.

3. Bus Interface

Cycle Qualification

One SN74F02N gate asserts FDC_CYCLE only while slot 1 and the lower byte lane are selected.

FDC_CYCLE = NOT (IO1_n OR LDS_n)

An upper-byte-only access reaches the motherboard timeout. A word access completes because it includes the lower lane, but only D7..D0 carry valid controller data. Firmware shall use byte accesses at odd addresses.

Read and Write Strobes

U_FDC_INV produces FDC_RW_n and FDC_CS_n. Two U_FDC_CTRL NAND gates convert the qualified processor cycle into the controller's active-low strobes.

FDC_RW_n = NOT R/W
FDC_CS_n = NOT FDC_CYCLE
FDC_RD_n = NOT (FDC_CYCLE AND R/W)
FDC_WR_n = NOT (FDC_CYCLE AND FDC_RW_n)

Fixed Completion Response

U_FDC_SEQ is a CD74HCT164E clocked at 5 MHz. Its serial inputs are high and its active-low clear connects to FDC_CYCLE. Three rising clock edges shift a high level to QC. This holds FDC_RD_n or FDC_WR_n active for at least two complete 200 ns clock periods before the adapter returns completion.

FDC_ACK_READY = U_FDC_SEQ.QC
FDC_DTACK_n   = NOT (FDC_CYCLE AND FDC_ACK_READY)

Releasing either IO1_n or LDS_n clears the sequencer asynchronously, negates the selected host strobe, and releases FDC_DTACK_n. A new access starts from the cleared state.

4. Register Map

Processor address lines A1..A3 become controller address bits 0 through 2. The canonical address for controller location n is $E20001 + 2n. Address lines A16..A4 do not enter the local decode, so the 16-byte pattern repeats throughout slot 1.

Firmware shall not access the reserved location or use writes that the table marks as undefined. The Tape Drive Register remains zero because neither installed device is a tape drive.

5. Clock, Reset, and Mode Straps

24 MHz Reference

Y_FDC is a 24 MHz parallel-resonant, fundamental-mode crystal between X1 and X2. The specified part is the YIC 24M20PI/49US in an HC-49/US package. C_FDC_X1 and C_FDC_X2 are 22 pF C0G capacitors from the corresponding crystal pins to ground, matching Intel's application circuit. Any substitute must have no more than 40 ohms series resistance, less than 5 pF shunt capacitance, and a total frequency error within +/-0.1%.

The oscillator requires 10 ms after +5 V reaches 4.5 V before the controller can rely on its internal timing. The motherboard's 250 ms power-on reset covers this interval.

Hardware Reset

One U_FDC_INV channel converts active-low PERIPH_RESET_n to the controller's active-high FDC_RESET. The 82077AA-1 requires 170 crystal periods, about 7.1 us, after its oscillator is stable. The processor RESET instruction supplies about 12.4 us through the peripheral-reset domain, and the power-on and manual-reset pulses are longer.

FDC_RESET = NOT PERIPH_RESET_n

Reset stops an active disk command and can corrupt a sector if it occurs during a write. Firmware must reinitialize the data rate, FIFO, mechanical timing, and non-DMA mode after every reset.

PS/2 Mode

IDENT connects to ground, MFM remains open, and INVERT connects to ground. The controller samples IDENT low and MFM high during hardware reset, selecting PS/2 mode. This mode exposes Status Registers A and B, keeps INT and DRQ enabled independently of the DOR DMA-gate bit, and makes DENSEL_n low at 500 kbit/s as expected by a PC 3.5-inch drive.

PLL0 connects to +5 V for floppy operation. DRV2 also connects to +5 V so Status Register A reports that the second drive is installed. DACK and TC connect to +5 V, their inactive level in PS/2 mode. DRQ remains unconnected.

6. Drive Interface

With INVERT grounded, the 82077AA-1 drives and receives the standard active-low floppy-cable signals directly. Ten 33 ohm series resistors sit at the controller outputs to damp cable edges.

RP_FDC_IN is a five-resistor isolated SIP network. Each 10 kohm resistor pulls one returned signal to +5 V at the controller end of the cable. Intel recommends about 10 kohms for PS/2-mode 3.5-inch drives because their outputs become high impedance when deselected.

The recommended network is the Bourns 4610X-102-103LF, a 10-pin SIP holding five isolated 10 kohm resistors. Any five-element isolated 10 kohm SIP with the same footprint is acceptable.

The D359M3D PC configuration puts disk-change on pin 34. No drive modification is required. The 82077AA-1 has no external READY input for its legacy polling sequence; it treats ready as asserted internally. Firmware uses disk-change, index, command results, and timeouts to detect missing or unusable media.

The required 1.44 MB format uses MFM at 500 kbit/s, 80 cylinders, two heads, 18 sectors per track, and 512 bytes per sector. Its exact formatted capacity is 1,474,560 bytes, or 1.40625 MiB. The D359M3D also supports 250 kbit/s media, but 720 KiB operation is optional software behavior rather than a board requirement. The 1 Mbit/s perpendicular mode is not used.

7. Signal Connector and Cable

J_FDC is one keyed, shrouded, 2-by-17, 2.54 mm motherboard header. Pin 3 is omitted as the polarization key. Every other odd-numbered pin is ground. The cable stays inside the enclosure and has one untwisted drive connector followed by a twist in conductors 10 through 16 and a final drive connector.

The recommended header is the Amphenol ICC 66506-019LF. Any keyed, shrouded, 2-by-17, 2.54 mm header with the same footprint and the pinout below is acceptable.

Both drives stay configured as PC drive select 1. The connector before the twist is controller drive 1. The final connector after the twist is controller drive 0 and the boot drive. The motor-enable conductors twist with the select conductors, so each DOR motor bit follows its assigned drive.

8. Drive Power

J_FDD0_POWER and J_FDD1_POWER are keyed four-contact mini-Berg power headers. Each connector has its own +5 V and +12 V resettable fuse. The D359M3D specification calls for +5 V only, so its +12 V contact draws no normal current. Supplying the standard +12 V contact keeps the motherboard connector compatible with ordinary 3.5-inch drive power cables.

The recommended header is the TE Connectivity 171825-4, a four-position keyed through-hole male header. Any four-contact keyed header with the same footprint and the pinout below is acceptable.

Each post-fuse +5 V branch has 470 uF and 100 nF to ground beside its connector. Each post-fuse +12 V branch has 47 uF and 100 nF. The D359M3D data sheet gives 1.6 W typical operating power and 0.04 W typical standby power from +5 V, corresponding to about 320 mA and 8 mA. The 1.10 A hold rating leaves room for motor startup current.

The fuses protect the connector branches; they do not set the system supply rating. The upstream rails, traces, and input connector must carry the sum of both drive branches and the rest of the computer. Drive power is not hot-pluggable.

9. Interrupts and Programmed I/O

The 82077AA-1 push-pull INT output connects directly to MC68901 GPIP5 as FDC_INT. The MFP detects its rising edge and supplies vector $47 during the processor's level-6 interrupt acknowledge. No pull-up is fitted.

Non-DMA mode uses INT and the Main Status Register's RQM bit for FIFO service. During a read, INT rises when the FIFO reaches its programmed service level or contains the last bytes of a sector. During a write, INT rises when the FIFO can accept data. It also rises when a seek or recalibrate completes and when a data command enters its result phase.

The interrupt handler reads the Main Status Register before choosing an action. When RQM and NON-DMA are set, it transfers bytes in the direction selected by DIO until RQM clears. A seek or recalibrate completion requires Sense Interrupt Status. A data-command result phase requires the command's complete result-byte sequence. The handler must not issue Sense Interrupt Status for a FIFO data request.

The CONFIGURE command enables the FIFO, disables legacy drive polling, enables implied seeks, and selects an eight-byte threshold. At 500 kbit/s the controller data sheet gives about 126.5 us between an eight-byte service request and FIFO overrun or underrun. The handler still transfers until RQM clears instead of assuming that every interrupt represents exactly eight bytes.

10. Firmware Contract

Initialization

1. Wait until the motherboard releases reset and the controller's 24 MHz oscillator has been stable for at least 10 ms.
2. Write the Digital Output Register with bit 2 high to release the controller core. Keep both motor bits low and select drive 0.
3. Write $00 to the Configuration Control Register for 500 kbit/s operation.
4. Issue CONFIGURE bytes $13, $00, $57, $00. This enables implied seeks, enables the FIFO, disables drive polling, selects an eight-byte threshold, and starts write precompensation at track 0.
5. Issue SPECIFY bytes $03, $DF, $11. At 500 kbit/s this selects a 3 ms step interval, 240 ms head-unload time, 16 ms head-load time, and non-DMA operation.
6. Recalibrate drive 0 and drive 1 separately. Complete each operation with Sense Interrupt Status and verify that the present cylinder is zero.

If firmware cannot issue CONFIGURE before the reset polling sequence raises INT, it shall issue four Sense Interrupt Status commands to drain the controller's queued reset status before continuing.

Drive Selection and Motors

A Digital Output Register value of $1C selects drive 0, releases controller reset, and runs motor 0. $2D does the same for drive 1. The DMA-gate bit in these compatibility values has no effect in PS/2 mode. Firmware shall wait at least 500 ms after starting a stopped motor before writing.

Firmware may leave one motor running while selecting the other drive by retaining the first motor-enable bit in the DOR. It shall turn each motor off after the final access.

Full-Sector Transfers

The board does not generate DMA acknowledge or terminal count. Firmware transfers complete 512-byte sectors and uses the command's EOT parameter to enter the result phase normally. For one sector, EOT equals the requested sector number. Multi-sector operations may end at sector 18. Partial-sector transfers are outside this hardware contract.

Before each FIFO access, firmware shall require RQM to be one and DIO to match the transfer direction. Every wait for RQM, INT, index, seek completion, or result bytes needs a finite software timeout. A timeout resets and reinitializes the controller before another command is attempted.

Required 1.44 MB Parameters

11. Package and Pin Maps

Intel 82077AA-1

Adapter Packages

Every 14-pin gate package uses pin 14 for +5 V and pin 7 for ground. Ground U_FDC_REQ pins 5, 6, 8, 9, 11, and 12; U_FDC_INV pins 9, 11, and 13; and U_FDC_CTRL pins 12 and 13. Leave their unused outputs open. U_FDC_SEQ pin 14 connects to +5 V and pin 7 to ground. Pins 1 and 2 connect to +5 V, pin 8 to MFP_CLK_5, pin 9 to FDC_CYCLE, and pin 5 produces FDC_ACK_READY. Its other outputs remain open.

12. Timing and Electrical Checks

The sequencer delay is 400 to 600 ns from cycle qualification before gate delay, below the motherboard's 51.1 us normal-cycle timeout.

Completion Release

U_FDC_CTRL adds at most 6 ns when releasing FDC_DTACK_n. The motherboard tree adds 5.3 ns in its group SN74F21, 5.3 ns in the final SN74F21, and 6.6 ns in the timeout mask. The 23.2 ns component total leaves 86.8 ns for routing and loading under the MC68EC000's 110 ns release limit.

U_FDC_CTRL release            6.0 ns maximum
group SN74F21                 5.3 ns maximum
final SN74F21                 5.3 ns maximum
timeout-mask SN74F32          6.6 ns maximum
------------------------------------------------
component total              23.2 ns
MC68EC000 limit             110.0 ns
board allowance              86.8 ns

Logic Levels and Loading

The 82077AA-1 host inputs use TTL thresholds: no more than 0.8 V for low and at least 2.0 V for high. Its host data outputs guarantee no more than 0.4 V at 12 mA and at least 3.0 V at a 4 mA source load.

C_FDC_FILTER connects directly between HIFIL and LOFIL. It has no ground connection. Use a 4.7 nF C0G or other low-leakage capacitor. Intel gives about 500 us settling time for 5 nF after a data-rate change, so firmware shall wait 1 ms before starting a transfer.

Each digital VCC pin has a 100 nF ceramic capacitor to its nearest ground pin. U_FDC also has 4.7 uF beside the package. FB_FDC_AVCC feeds AVCC from +5 V, with 100 nF and 1 uF returned to AVSS. Every adapter IC has a 100 nF capacitor at its supply pins.

13. Parts Added

Intel documented the enhanced 82077AA feature set by the first quarter of 1991. The 74F00, 74F02, and 74F04 appear in Fairchild's 1980 FAST data book, and HCT164 logic was established during the 1980s. Later data-sheet revisions do not change the family-date rule. The two D359M3D drives are user-selected parts.

14. Board Layout

• Put J_FDC at the board edge facing the drive bays. Mark pin 1 and the missing pin 3 on copper and silkscreen, then verify the key against the cable socket.
• Put the ten 33 ohm resistors beside U_FDC and the five input pull-ups at the controller end of the cable.
• Keep Y_FDC, both 22 pF capacitors, and their ground returns inside a small loop at pins 33 and 34.
• Put C_FDC_FILTER directly between pins 37 and 38. Keep both filter pins short, clean, and away from the crystal and cable traces.
• Put FB_FDC_AVCC and the AVCC capacitors beside pins 45 and 46. Join AVSS to the plane without sharing a narrow drive-current return.
• Route every floppy-cable signal beside its odd-pin ground return. Avoid stubs between U_FDC, the pull-ups, and J_FDC.
• Place each pair of resettable fuses beside its power header. Use wide upstream and post-fuse copper.
• Mark +5 V, both ground pins, and +12 V at each mini-Berg header. Check the footprint from the cable mating face.
• Measure the loaded MFP_CLK_5 waveform at U_FDC_SEQ and include the route and probe in the MFP clock-load check.
• Measure the routed FDC_DTACK_n release path and keep its board contribution below 86.8 ns.

15. Assembled-System Acceptance

16. Internal Signal Reference

17. Sources

• Intel, 82077AA CHMOS Single-Chip Floppy Disk Controller, order number 290166-007, May 1994. Host registers, PS/2 mode, FIFO behavior, drive interface, electrical limits, and timing.
• Mitsumi, 3.5-inch Compact Floppy Disk Drive D359M3D, D353M3D. Capacity, data rates, access times, +5 V power, and dimensions.
• Motorola, M68000 User's Manual, processor bus cycles and timing.
• Texas Instruments, SN74F00, SN74F02, SN74F04, and CD74HCT164 data sheets.
• Fairchild, FAST Data Book, 1980. Family-date reference for the selected FAST gates.
• Littelfuse, RXEF Series PolySwitch Resettable Devices. Drive-branch fuse ratings.