MC68901 MFP

1. Purpose and Scope

The MC68901 combines the system interrupt controller, four timers, an eight-bit general-purpose port, and one full-duplex USART. This page fixes every motherboard connection to the device and its two external ports. Software policy and firmware initialization are outside its scope.

Signal names ending in _n, and signal names written with a leading slash, are active low. The board uses +5 V logic and through-hole packages. Every IC family selected here existed before 1994.

2. Architecture

MC68EC000 lower byte                     external ports and interrupt sources

D7..D0 <------------------> MC68901P
A5..A1 -------------------> RS5..RS1       SO ----> MAX232 ----> DE-9 TXD
IO0_n --------------------> /CS            SI <---- MAX232 <---- DE-9 RXD
LDS_n --------------------> /DS            I0 ----> MAX232 ----> DE-9 RTS
R/W ----------------------> R/W            I6 <---- MAX232 <---- DE-9 CTS
PERIPH_RESET_n -----------> /RESET
MFP_CLK_2P5 --------------> CLK            I7 <---> PS/2 clock
IACK_L6_n ----------------> /IACK          I1 <---> PS/2 data
MFP_IRQ_n ----------------> CPU level 6    I5 <---- floppy INT
MFP_DTACK_n --------------> /DTACK tree    I4 <---- MIDI /IRQ
                                           I3 <---- RTC /IRQ
2.4576 MHz crystal -------> XTAL1/XTAL2    I2 <---- VGA VSYNC
TDO ----------------------> RC and TC
Timer C ------------------> 100 Hz system tick

The USART remains a TTL-level circuit inside the MFP. The MAX232 supplies the voltage conversion and inversion required at the RS-232 connector. The PS/2 lines connect to GPIP pins through series resistors and use direction switching to reproduce open-collector signaling.

3. Bus Interface

The motherboard slot decoder already excludes CPU-space cycles, so IO0_n and /IACK cannot be asserted together. During interrupt acknowledge the MC68EC000 asserts both data strobes; LDS_n therefore supplies the MFP's required /DS strobe while IACK_L6_n selects the acknowledge operation.

The MFP's /DTACK output drives high before entering its high-impedance state. A 4.7 kohm pull-up on MFP_DTACK_n keeps the completion-tree input inactive while the MFP is not driving it. The same physical net serves normal register cycles and vectored acknowledge cycles.

Addressing Rules

Software accesses the MFP as bytes at odd addresses. A lower-byte access asserts LDS_n; an upper-byte-only access leaves the MFP unselected and reaches the motherboard bus timeout. A word read also asserts LDS_n and completes, but only D7..D0 contain MFP data, so word accesses are not part of the interface contract.

Address lines A16..A6 do not enter the local decode. The register block repeats every 64 bytes throughout slot 0. The table below names the canonical copy beginning at $E00000.

4. Register Map

The MC68901 contains 24 directly addressed eight-bit registers. The register functions and addresses come from the MC68901 register map; this table does not prescribe their firmware values.

Offsets $31-$3F select no defined MC68901 register. They are not motherboard registers even though the MFP still owns the slot.

5. Clock and Reset

MFP Bus Clock

The original MC68901P accepts a 1 to 4 MHz CLK. A SN74HCT74N, U_MFP_CLK, divides the existing 10 MHz INT_CLK by four and produces MFP_CLK_2P5. Each half is a toggle stage with its complementary output connected to its D input. All asynchronous preset and clear inputs connect to +5 V.

INT_CLK -- divide by 2 --> MFP_CLK_5 -- divide by 2 --> MFP_CLK_2P5

MFP_CLK_2P5 frequency = 10 MHz / 4 = 2.5 MHz
MFP clock period       = 400 ns
MFP high and low time  = 200 ns nominal

MFP_CLK_5 also drives one SN74F04 input in the MIDI local clock buffer and one CD74HCT164 clock input in the floppy bus adapter. The MIDI buffer isolates its divider and bus-adapter clocks from this net.

The 400 ns period lies between the MC68901's 250 ns minimum and 1000 ns maximum. Its nominal 200 ns high and low times exceed the 110 ns minimum.

Timer Crystal

Y_MFP_TIMER is a CTS MP024S: a 2.4576 MHz parallel-resonant, fundamental-mode AT-cut crystal between XTAL1 and XTAL2, specified for a 32 pF load and no more than 300 ohms series resistance. One 56 pF capacitor connects from each crystal pin to ground, which with a few picofarads of stray capacitance presents the specified load.

Reset

PERIPH_RESET_n connects directly to the MC68901 /RESET pin. The MFP requires at least 2 us low. The motherboard reset circuit supplies the long power-on and manual-reset pulse and at least 12.4 us when the processor executes RESET.

Reset stops all timers, disables both USART directions and every interrupt channel, clears pending interrupts, places all GPIP pins in high-impedance input mode, drives the timer outputs low, and negates the external handshake signals. The vector register resets to $00, so an unprogrammed MFP answers an acknowledge cycle with vector number $0F, the processor's uninitialized-interrupt vector. Firmware writes the vector register before it enables any channel. TADR, TBDR, TCDR, TDDR, UDR, and most TSR state do not receive a defined data value from reset.

6. Interrupts

The MFP presents all sixteen internal channels at CPU level 6. Its open-drain /IRQ output is MFP_IRQ_n and has a 4.7 kohm pull-up to +5 V. IACK_L6_n connects to /IACK, IEI connects to ground, and IEO is open because no second vectored device follows the MFP.

The system reserves vector base $40. The MFP supplies the channel number in the low nibble, producing vectors $40-$4F. Channel 15 has the highest priority and channel 0 the lowest. The programmable enable, pending, mask, and in-service state remains visible through IERA/B, IPRA/B, IMRA/B, and ISRA/B.

Interrupts owns the CPU-side priority encoder, level-6 acknowledge decode, autovectors, and spurious-cycle termination. This page owns the MFP's channel and pin assignments.

7. Timers

All four timers count the 2.4576 MHz crystal through a programmable prescaler. Timers A and B remain available as internal delay timers. Their unused TAI and TBI inputs connect to ground, and TAO and TBO go to labeled test pads.

Timer C System Tick

Timer C uses the divide-by-100 prescaler and a data value of 246 ($F6). A timeout occurs at 99.9024 Hz, a period of 10.0098 ms. This is the board's nominal 100 Hz system tick. The TCO pin toggles on each timeout and goes to a labeled test pad; the interrupt channel supplies the tick to the processor.

Timer C timeout = 2,457,600 / (100 * 246)
                = 99.9024 Hz

Timer D Baud Clock

TDO connects to both RC and TC, giving the receiver and transmitter the same clock. Timer D uses the divide-by-four prescaler. In the USART's divide-by-16 asynchronous mode, the timer data values below produce the standard rates.

baud = 2,457,600 / (2 * 4 * TDDR * 16)
     = 19,200 / TDDR

TDDR = 0 represents a count of 256.

8. RS-232 Port

U_RS232 is an original-family MAX232CPE in a 16-pin plastic DIP. It provides two drivers, two receivers, and the charge pumps needed to run the port from +5 V. Its two channels carry TXD/RXD and RTS/CTS. The selected timer clocking limits the port to 19,200 baud, below the MAX232's 120 kbit/s rating.

A 10 kohm pull-up on T1IN holds TXD in the RS-232 mark state while the MFP's SO output is high impedance after reset. A second 10 kohm pull-up on T2IN holds RTS deasserted while GPIP0 is an input. Because the MAX232 inverts control signals, driving GPIP0 low asserts RTS at the connector and driving it high deasserts RTS.

RTS and CTS have fixed electrical paths but no automatic connection to the USART state machine. GPIP0 controls RTS, and GPIP6 reports CTS and can raise an interrupt. CTS does not gate SO in hardware.

Charge-Pump Connections

DE-9 DTE Connector

J_RS232 is a male DE-9 receptacle at the board edge. The recommended part is the Amphenol ICC LD09P33E4GV00LF, a right-angle through-hole male DE-9 with board locks. Any male DE-9 with the same footprint and the pinout below is acceptable.

9. PS/2 Keyboard Port

GPIP7 carries keyboard clock and GPIP1 carries keyboard data. Each motherboard node has a 4.7 kohm pull-up to +5 V and reaches the mini-DIN connector through a 220 ohm series resistor. The resistors limit contention current if either endpoint drives at the wrong time.

An MFP GPIP pin releases a PS/2 line when its DDR bit is zero. It pulls the line low when its GPDR bit is zero and its DDR bit is one. The circuit never requires a driven high level, so it preserves the PS/2 wired-AND behavior. Reset sets the DDR to input and releases both lines. GPIP7 detects falling clock edges while the keyboard is sending; GPIP1 supplies the data level.

J_PS2 is a female mini-DIN-6 receptacle at the board edge. The recommended part is the Kycon KMDGX-6S-BS, a through-hole shielded mini-DIN-6 with board locks. Any mini-DIN-6 receptacle with the same footprint and the pinout below is acceptable.

A 100 nF ceramic capacitor and a 10 uF electrolytic capacitor connect from the fused +5 V keyboard supply to ground beside the connector.

10. GPIP Assignment

GPIP4 and GPIP3 each have their own pull-up because their source outputs are open drain. The floppy and VGA outputs are push-pull and need no pull-up. The PS/2 pull-ups belong to the keyboard interface, and the RTS pull-up belongs to the MAX232 input.

The YMF262 timers use status polling. The OPL3 circuit does not share a GPIP input with any source in this table.

11. Package and Pin Map

MC68901P

MFP Clock Divider

12. Timing and Electrical Checks

Bus Response

The asynchronous MC68901 samples /CS or /IACK against its local clock. If a request misses one falling edge, the next falling edge arrives 400 ns later. The MFP then asserts /DTACK within 220 ns. A worst-phase request therefore reaches the raw MFP acknowledgement within about 620 ns, far inside the motherboard's 51.1 us normal-cycle timeout.

On release, the MC68901 drives /DTACK high within 60 ns after /CS or /DS rises. The completion tree adds 5.3 ns through the group SN74F21, 5.3 ns through the final SN74F21, and 6.6 ns through the SN74F32 timeout mask. The 77.2 ns total leaves 32.8 ns for routed delay and loading under the MC68EC000's 110 ns acknowledgement-release limit.

MFP /DTACK release          60.0 ns maximum
group SN74F21               5.3 ns maximum
final SN74F21               5.3 ns maximum
SN74F32 timeout mask        6.6 ns maximum
------------------------------------------------
component total            77.2 ns
MC68EC000 limit           110.0 ns
board allowance            32.8 ns

Logic Levels and Fanout

The MAX232 supply range is 4.5 to 5.5 V, which contains the motherboard's 4.75 to 5.25 V rail. Its RS-232 receivers tolerate inputs up to +/-30 V. The selected 1 uF charge-pump capacitors are the value specified for the original MAX232.

13. Parts Added

U_MFP, U_MFP_CLK, and U_RS232 belong to device families documented before 1994. Each IC has a 100 nF ceramic bypass capacitor at its supply pins. U_MFP and U_MFP_CLK also have a 1 uF capacitor beside the package, following the motherboard convention.

14. Board Layout

• Place the two 56 pF crystal capacitors beside MC68901 pins 17 and 18. Keep the crystal loop short and away from clock, bus, and charge-pump routes.
• Place all four 1 uF MAX232 charge-pump capacitors beside their pin pairs. Keep V+ and V- away from the crystal and PS/2 inputs.
• Put the RS-232 and PS/2 connectors at the board edge. Route their shell and ground returns to the ground plane at the entry point.
• Keep MFP_CLK_2P5, TDO, PS/2 clock, and the three open-drain interrupt routes short. Route MFP_CLK_5 directly from U_MFP_CLK to the MIDI local clock buffer and floppy response sequencer without long stubs.
• After routing, keep the INT_CLK branch at or below 50 pF and the added address and data pin load inside the limits in Bus and Decode.
• Measure MFP_CLK_2P5 at MC68901 pin 35 after layout. Its period must stay between 250 ns and 1000 ns, each high and low pulse must be at least 110 ns, and each edge must be no longer than 15 ns.
• Measure the routed /DTACK release path after layout and keep its board contribution below the 32.8 ns allowance.

15. Internal Signal Reference

16. Sources

• Motorola, MC68HC901 Multi-Function Peripheral User's Manual. The manual identifies the MC68HC901 as the HCMOS version of the MC68901 and carries the common register, pin, timer, USART, and interrupt definitions.
• Motorola, MC68901 Multi-Function Peripheral, January 1984. This is the source for the original NMOS part's 1 to 4 MHz clock limits, reset timing, electrical limits, bus timing, crystal circuit, and MC68901P ordering code.
• Maxim Integrated, MAX220-MAX249 +5 V-Powered, Multichannel RS-232 Drivers/Receivers. This is the source for the MAX232CPE ordering code, pinout, and charge-pump circuit.
• Texas Instruments, MAX232 Dual EIA-232 Drivers and Receivers. This is the source for the +5 V supply range, input limits, 1 uF original-MAX232 circuit, and 120 kbit/s rating.
• Motorola, M68000 User's Manual, sections 3.1 through 3.3 and 5.1.4.
• Texas Instruments, SN74HCT74 Dual D-Type Flip-Flops.