MC6850 MIDI

1. Purpose and Scope

The MC6850 supplies one full-duplex asynchronous serial channel for MIDI. The board has a galvanically isolated MIDI input, a software controlled MIDI output, and a hardware THRU output that copies the isolated input while the computer is powered. The THRU path does not pass through the ACIA or depend on firmware.

The Memory Map owns the slot and register addresses. Bus and Address Decode owns IO5_n, the completion tree, and timeout behavior. The MFP owns GPIP4 and vector $46. The MFP clock section owns MFP_CLK_5.

Signal names ending in _n, and signal names written with a leading slash, are active low. The board uses +5 V logic and through-hole packages. Every IC family and ordering code selected here was documented before 1994.

2. Architecture

MC68EC000 lower byte                 MC6850P and MIDI ports

D7..D0 <--------------------------> D7..D0
       +----> U_MIDI_RDATA D inputs
       <---- U_MIDI_RDATA Q outputs after an ACIA read
A1 --------------------------------> RS
R/W -------------------------------> R/W
IO5_n + LDS_n --> MIDI_CYCLE ------> request synchronizer
MFP_CLK_5 --> local buffer --------> synchronizer and adapter clocks
             +-- divide by 10 -----> MIDI_CLK_500K
                                     +--> MC6850 E, Tx CLK, Rx CLK
request --> SELECT --> DONE --> ACK_READY --> MIDI_DTACK_n
                                      |
MC6850 /IRQ -- 4.7 kohm pull-up ------+--> MC68901 GPIP4

MIDI IN --> 6N138 --> two LS14 stages --+--> MC6850 Rx Data
                                         +--> LS07 --> MIDI THRU
MC6850 Tx Data ------------------------------> LS07 --> MIDI OUT

The MC68EC000 lacks the M6800-family E, VMA, and VPA peripheral interface. The adapter synchronizes each processor request to a continuous local enable clock. It captures read data at the end of the MC6850 cycle and holds that byte on the processor bus before returning MIDI_DTACK_n.

3. Bus Interface

Cycle Qualification

One SN74F02N gate, U_MIDI_REQ, asserts MIDI_CYCLE only while slot 5 and the lower byte lane are selected.

MIDI_CYCLE = NOT (IO5_n OR LDS_n)

An upper-byte access leaves MIDI_CYCLE low and reaches the motherboard timeout. A word access includes the lower lane and completes, but only D7..D0 contain valid data. Software shall use byte accesses at odd addresses.

MC6850 Selection

MC6850 CS0 and CS1 connect to +5 V. /CS2 receives MIDI_ACIA_CS_n. U_MIDI_CS is one SN74F32N OR gate driven by the complementary SELECT output and DONE.

MIDI_ACIA_CS_n = (NOT MIDI_SELECT) OR MIDI_DONE

Selection begins after one falling edge of MIDI_CLK_500K and ends after the next falling edge. The MC6850 sees a complete low and high enable phase with address, direction, and write data held by the waiting processor cycle.

Read-Data Hold Register

U_MIDI_RDATA is an SN74HCT574N. Its D inputs and Q outputs connect bit-for-bit to processor D7..D0. The rising clock input receives MIDI_E_n, so it captures the MC6850 byte just after each falling edge of E. U_MIDI_READ_OE, one SN74F10N gate, enables the outputs only after a selected read reaches DONE.

MIDI_READ_OE_n = NOT (MIDI_DONE AND R/W AND MIDI_CYCLE)

The MC6850 and U_MIDI_RDATA can drive the bus together briefly after the completion edge. Both drive the byte that the register captured. The ACIA then enters its high-impedance state while the register holds the byte through processor termination. During writes, U_MIDI_RDATA does not drive the bus.

4. Adapter Sequence

U_MIDI_SYNC is an SN74HCT74N. Its first flip-flop samples MIDI_CYCLE on MIDI_CLK_5; its second stage produces MIDI_REQ_SYNC. Both asynchronous clears connect to MIDI_CYCLE, so releasing the processor cycle clears the request without waiting for a clock edge.

U_MIDI_SEQ is a second SN74HCT74N. Both flip-flops clock on MIDI_E_n, the inverted 500 kHz enable clock. The first D input is high and produces SELECT. The second D input receives SELECT and produces DONE one enable period later. Their clears connect to MIDI_REQ_SYNC.

U_MIDI_ACK is one half of a third SN74HCT74N. It samples DONE on MIDI_CLK_5 and produces MIDI_ACK_READY. Its asynchronous clear connects directly to MIDI_CYCLE. The extra 5 MHz stage gives U_MIDI_RDATA time to enable before the motherboard sees an acknowledgement.

U_MIDI_ACK_GATE is one SN74F00N NAND gate. Raw cycle qualification keeps the completion response inactive outside slot 5 and releases it promptly when LDS_n rises.

MIDI_DTACK_n = NOT (MIDI_ACK_READY AND MIDI_CYCLE)

5. Register Map

Address lines A16..A2 do not enter the local decode. The two-register pattern repeats every four bytes throughout slot 5. The addresses above are the canonical copy used by firmware.

/CTS and /DCD connect to ground. The transmitter remains clear to send and the receiver remains enabled. /RTS is unused and has no board connection.

6. Clock and Reset

U_MIDI_INV channel 1 is one SN74F04N inverter. It takes MFP_CLK_5 from the first stage of the MFP clock divider and drives the MIDI-local MIDI_CLK_5 net. U_MIDI_CLK is an SN74LS390N wired as divide by 5 followed by divide by 2. Its final divide-by-2 output supplies a symmetrical 500 kHz waveform.

MFP_CLK_5 -- local buffer --> MIDI_CLK_5
MIDI_CLK_5 -- divide by 5 --> MIDI_CLK_DIV5
MIDI_CLK_DIV5 -- divide by 2 --> MIDI_CLK_500K

MIDI_CLK_500K --> MC6850 E, Tx CLK, and Rx CLK
MC6850 divide ratio = 16
MIDI bit rate = 31.25 kbit/s

U_MIDI_CLK pin 4, 1CLKB, receives MIDI_CLK_5. Pin 7, 1QD, feeds pin 1, 1CLKA. Pin 3, 1QA, produces MIDI_CLK_500K. Pin 2, 1CLR, is grounded. The unused second counter has both clock inputs and its clear input grounded; its outputs remain unconnected.

ACIA Reset

The MC6850 has no reset pin. Its control-register divide field must be written as 11 after power-up and after every processor RESET sequence. Firmware writes $03 to $EA0001 before it writes the operating configuration.

The clock divider runs whenever +5 V and MFP_CLK_5 are present. Adapter state clears whenever no MIDI bus cycle is active. The MC6850 remains in an unspecified power-up state until firmware issues the master-reset write.

7. Programming Rules

The normal operating control byte is $95. It selects the divide-by-16 clock, 8-N-1 framing, inactive transmitter interrupts, low /RTS, and enabled receiver interrupts.

Firmware reads the status register before the data register. RDRF identifies a current received byte; FE, OVRN, and PE describe that receive state. Firmware writes the transmit data register only while TDRE is set. Changing word format or clock division while a byte is in flight can corrupt that byte.

A polling-only configuration uses $15. Transmitter interrupts stay disabled in both configurations because TDRE is normally high whenever the transmitter is idle and would otherwise hold /IRQ low.

8. Interrupts

MC6850 pin 7 is an active-low open-drain output. R_MIDI_IRQ is a 4.7 kohm pull-up from MIDI_IRQ_n to +5 V. The same net connects to MC68901 GPIP4. The MFP detects the falling edge and supplies vector $46 during the level-6 acknowledge cycle.

With control byte $95, a full receive register or an overrun can request service. DCD is held low. The handler reads status, reads the receive data register when RDRF or an error is present, and returns after the enabled condition has cleared.

MIDI THRU remains active while the MC6850 interrupt is pending. A slow handler can overrun the ACIA receive register, but it does not stop the electrical copy from MIDI IN to MIDI THRU.

9. MIDI IN

J_MIDI_IN is a 5-pin, 180-degree DIN female connector. Pin 4 reaches U_MIDI_OPTO pin 2, the 6N138 LED anode, through R_MIDI_IN, 220 ohms. DIN pin 5 connects to U_MIDI_OPTO pin 3, the cathode. D_MIDI_IN is a 1N4148 across the LED with its cathode at pin 2 and anode at pin 3.

J_MIDI_IN pin 4 -- 220 ohms --+--> 6N138 pin 2, anode
                              |
                         1N4148 reverse clamp
                              |
J_MIDI_IN pin 5 --------------+--> 6N138 pin 3, cathode

6N138 pin 8 ----------------------> +5 V
6N138 pin 5 ----------------------> ground
6N138 pin 6 -- 2.2 kohm pull-up --> MIDI_RX_OPTO_n
6N138 pin 7 -- 47 kohm -----------> ground

MIDI_RX_OPTO_n --> LS14 --> LS14 --> MIDI_RX_DATA

U_MIDI_OPTO pins 1 and 4 remain open. C_MIDI_OPTO, 100 nF, connects between pins 8 and 5 at the package. R_MIDI_BASE uses the 6N138 datasheet's 47 kohm gain-warning boundary while reducing stored charge.

Two channels of U_MIDI_SCHMITT, an SN74LS14N, square the optocoupler output and restore its polarity. Current through the optocoupler makes MIDI_RX_DATA low. The net drives MC6850 Rx Data and one U_MIDI_DRIVER input. Pins 1, 2, and 3 of J_MIDI_IN have no DC connection to motherboard ground.

10. MIDI OUT and THRU

U_MIDI_DRIVER is an SN74LS07N. One non-inverting open-collector channel takes MC6850 Tx Data and sinks the MIDI OUT loop. A second channel takes MIDI_RX_DATA and sinks the MIDI THRU loop. Logical zero turns the selected output transistor on, matching MIDI's current-on zero state.

+5 V -- 220 ohms --> J_MIDI_OUT pin 4
J_MIDI_OUT pin 5 -- 220 ohms --> LS07 output
MC6850 Tx Data ----------------> LS07 input

+5 V -- 220 ohms --> J_MIDI_THRU pin 4
J_MIDI_THRU pin 5 -- 220 ohms --> LS07 output
MIDI_RX_DATA ------------------> LS07 input

The four output resistors are 220 ohms, 5%, 0.25 W. Each output drives one MIDI input. Four unused SN74LS07 inputs connect to ground and their outputs remain open. MIDI OUT idles with Tx Data high. MIDI THRU follows the isolated input even while the ACIA is reset or software is not reading it.

11. Connector Pinout

J_MIDI_IN, J_MIDI_OUT, and J_MIDI_THRU are labeled 5-pin, 180-degree DIN female receptacles. Connector drawings can show pin numbers from the mating face or solder side. The schematic symbol and footprint shall use the manufacturer's numbering.

The recommended part is the CUI Devices SDS-50J, a through-hole 5-pin 180-degree DIN receptacle, used three times. Any 5-pin 180-degree DIN receptacle with the same footprint is acceptable.

12. Package and Pin Maps

MC6850P

6N138

Adapter Packages

Unused FAST gate inputs connect to ground. The unused U_MIDI_ACK half has D and CLK grounded and both asynchronous inputs tied high.

Sequential Logic Pins

Clock and Gate Pins

Every 14-pin gate package uses pin 14 for +5 V and pin 7 for ground. Unused input pins are grounded: U_MIDI_REQ pins 5, 6, 8, 9, 11, and 12; U_MIDI_INV pins 5, 9, 11, and 13; U_MIDI_CS pins 4, 5, 9, 10, 12, and 13; U_MIDI_READ_OE pins 1, 2, 9, 10, 11, and 13; U_MIDI_ACK_GATE pins 4, 5, 9, 10, 12, and 13; U_MIDI_SCHMITT pins 5, 9, 11, and 13; and U_MIDI_DRIVER pins 5, 9, 11, and 13. Their unused outputs remain unconnected.

13. Timing and Electrical Checks

The installed master oscillator has a tolerance of +/-100 ppm before aging. Division preserves that relative tolerance, so the nominal 31.25 kbit/s stream remains inside MIDI's +/-1% rate limit.

Bus Response

Request synchronization takes at most two 5 MHz periods plus phase alignment. Waiting for the first 500 kHz falling edge takes less than one enable period, the selected ACIA cycle takes one more period, and ACK_READY takes no more than one 5 MHz period after DONE. The conservative logic-only bound is 4.6 us before gate and routing delay, below the motherboard's 51.1 us normal-cycle timeout.

two 5 MHz synchronizer periods        0.4 us
wait to first 500 kHz falling edge   2.0 us
one selected MC6850 enable period    2.0 us
ACK_READY registration               0.2 us
------------------------------------------------
conservative phase bound             4.6 us

On release, U_MIDI_ACK_GATE adds at most 6 ns before MIDI_DTACK_n rises. The completion tree adds 5.3 ns in its group SN74F21, 5.3 ns in the final SN74F21, and 6.6 ns in the timeout-mask SN74F32. The 23.2 ns component total leaves 86.8 ns for routed delay and loading under the MC68EC000's 110 ns limit.

U_MIDI_ACK_GATE release       6.0 ns maximum
group SN74F21                5.3 ns maximum
final SN74F21                5.3 ns maximum
timeout-mask SN74F32         6.6 ns maximum
------------------------------------------------
component total             23.2 ns
MC68EC000 limit            110.0 ns
board allowance             86.8 ns

MC6850 read data is valid no later than 320 ns after E rises on the 1.0 MHz grade. The 1 us high phase leaves about 680 ns before E falls, so the data is settled well before the capture edge.

The capture edge is the problem. U_MIDI_INV inverts MIDI_CLK_500K into MIDI_E_n in up to 6.0 ns (SN74F04 tPLH), so U_MIDI_RDATA clocks that long after E falls. The MC6850 guarantees read data for only 10 ns after E falls, and the SN74HCT574 requires 5 ns of hold after its rising clock edge. The component-only hold margin is therefore negative:

MC6850 data hold after E falls      10.0 ns
U_MIDI_INV SN74F04, tPLH            -6.0 ns
SN74HCT574 data hold requirement    -5.0 ns
------------------------------------------------
component hold margin               -1.0 ns

Open item. This capture is not proven, and board delay only makes it worse. Confirm the MC6850P tDDR and tDHR figures against the 1.0 MHz column of the device data sheet, then close the margin before fabrication. The straightforward fixes are to clock U_MIDI_RDATA directly from MIDI_CLK_500K's falling edge instead of from the inverted copy, or to capture one MIDI_CLK_5 period earlier while E is still high. Section 13 numbers otherwise use the 1.0 MHz column throughout, which is what the E-cycle and serial-clock rows above already assume.

MIDI Current Loops

A complete 5 V MIDI loop contains three 220 ohm resistors. At nominal values and the 6N138 typical 1.4 V LED drop, the current is about 5.45 mA. At 4.75 V, 5% high resistors, and the 1.7 V maximum LED drop, it remains about 4.40 mA. The 6N138 guarantees TTL-load operation at 1.6 mA.

I nominal = (5.00 V - 1.40 V) / (3 * 220 ohms) = 5.45 mA
I low     = (4.75 V - 1.70 V) / (3 * 231 ohms) = 4.40 mA

Shorting an output signal pin to ground puts at most 5.25 V across one 209 ohm minimum resistor. The resulting 25.1 mA and 132 mW remain below the resistor's 0.25 W rating. The SN74LS07 output can sink the normal loop current and is rated for 40 mA low-state current.

14. Parts Added

Motorola documented the MC6850 revision used here in 1985. Texas Instruments documented the SN74LS390 in 1976, the SN74HCT74 in 1982, the SN74HCT574 in 1984, the FAST gates in 1987, and the SN74LS07 in 1990. Hewlett-Packard's 1978 optoelectronics catalog includes the 6N138. Each IC has a 100 nF ceramic bypass capacitor at its supply pins. U_MIDI_ACIA, U_MIDI_CLK, and U_MIDI_OPTO also have a 1 uF local capacitor beside the package.

15. Board Layout

• Put the three DIN connectors at the board edge and verify every footprint pin number against the mating-face drawing. Mark IN, OUT, and THRU on the silkscreen.
• Decide the chassis and shield scheme during board layout. MIDI_OUT_SHIELD, MIDI_THRU_SHIELD, and the three connector-shell pads may remain open or receive the board's chosen chassis or RF connection. Do not give J_MIDI_IN pin 2 or its shell a direct DC path to logic ground.
• Place U_MIDI_OPTO, D_MIDI_IN, and R_MIDI_IN beside J_MIDI_IN. Keep every isolated input-side trace away from motherboard-ground copper across the optocoupler isolation boundary.
• Place each OUT and THRU 220 ohm resistor beside its connector or driver. Keep the two current-loop traces paired and away from MIDI_RX_OPTO_n.
• Route MFP_CLK_5 only to U_MIDI_INV. Keep MIDI_CLK_5, MIDI_CLK_500K, and MIDI_E_n short and free of long test-point stubs.
• Measure the added MFP_CLK_5 load and the four-load MIDI_CLK_5 branch. Verify clean threshold crossings at U_MIDI_CLK, U_MIDI_SYNC, and U_MIDI_ACK.
• Measure MIDI_CLK_500K at MC6850 pins 3, 4, and 14. Each high and low pulse must exceed 600 ns, and the frequency must remain within the MIDI +/-1% limit.
• Measure the 6N138 and two LS14 stages with a 31.25 kbit/s test stream. Each final MIDI_RX_DATA edge must complete in less than 2 us, and THRU must preserve valid bit widths.
• Include U_MIDI_ACIA and U_MIDI_RDATA in the processor data-bus capacitance total. Check read-bus overlap at the second E falling edge and confirm that both devices drive the same captured value.
• Measure the E-falling-to-U_MIDI_RDATA clock path against the MC6850 data hold time. The component-only margin is negative, so resolve the open item in section 13 before committing the layout.
• Measure the routed MIDI_DTACK_n release path and keep its board contribution below 86.8 ns.
• Place every 100 nF capacitor at its IC supply pins. Put the 1 uF capacitors beside U_MIDI_ACIA, U_MIDI_CLK, and U_MIDI_OPTO.

16. Internal Signal Reference

17. Sources

• Motorola, MC6850 Asynchronous Communications Interface Adapter, 1985. Device operation, pinout, registers, electrical limits, and bus and serial timing.
• Motorola, M68000 User's Manual, sections 3.7, 5.1, 10.13, and 10.14.
• MIDI Manufacturers Association and AMEI MIDI Committee, MIDI 1.0 Electrical Specification Update, 2014. The 5 V circuit retains the original 220 ohm transmitter values, 5 mA loop, 8-N-1 format, DIN pinout, receiver isolation, and hardware THRU behavior.
• Hewlett-Packard, Optoelectronics Designer's Catalog, 1978. Historical 6N138 data and switching guidance.
• Broadcom, 6N138/6N139 Low Input Current, High Gain Optocouplers. Current electrical, package, bypass, and base-resistor data for the period 6N138 family.
• Texas Instruments, SN74LS390 Dual 4-Bit Decade Counter, October 1976, revised March 1988.
• Texas Instruments, SN74LS07, SN74LS14, SN74HCT74, and SN74HCT574 data sheets.
• Texas Instruments, SN74F00, SN74F02, SN74F04, SN74F10, and SN74F32 data sheets.