Memory Map

This document describes how the computer divides its 16 MiB address space among RAM, expansion memory, CL-GD5428 video memory, I/O devices, and firmware. Return to the main page.

The revision 1.1 address specification is frozen. This document may be corrected or expanded without a new revision. Any change to an address range, slot assignment, or register address requires a new memory map revision.

Document status
Revision 1.1; the address specification is frozen
CPU
MC68EC000FN10
Address bus
24-bit (16 MiB address space)
Data bus
16-bit
Main RAM
4 MiB of FPM DRAM
Firmware ROM
128 KiB, 16-bit wide, always read-only, built from four AT28C256-15PU EEPROMs
MIDI interface
MC6850 ACIA
Video controller
CL-GD5428 VGA controller with swapped byte lanes for the MC68EC000's big-endian bus and 2 MiB of video RAM
Floppy controller
Intel 82077AA-1 with two Mitsumi D359M3D drives

1. Main Memory Map

The top 2 MiB of the address space contains I/O devices and the firmware EEPROM. Each remaining region is 2 MiB wide.

Complete 24-bit address space
Start End Size Function Notes
$000000 $1FFFFF 2 MiB DRAM bank 0 The boot ROM alias temporarily replaces the first 128 KiB after reset.
$200000 $3FFFFF 2 MiB DRAM bank 1 The second 2 MiB DRAM bank. Its last 64 KiB is BIOS scratch memory.
$400000 $5FFFFF 2 MiB Expansion slot 1 memory Fixed EXP_MEM2_n window for front slot 1.
$600000 $7FFFFF 2 MiB Expansion slot 2 memory Fixed EXP_MEM3_n window for front slot 2.
$800000 $9FFFFF 2 MiB CL-GD5428 VGA host-memory window Mapped one-to-one onto the CL-GD5428 linear display-memory aperture. The board has 2 MiB of video RAM, so the window is fully populated.
$A00000 $BFFFFF 2 MiB Unimplemented EXP_MEM5_n does not reach either slot.
$C00000 $DFFFFF 2 MiB Unimplemented EXP_MEM6_n does not reach either slot.
$E00000 $FFFFFF 2 MiB I/O and firmware Divided into sixteen 128 KiB slots, listed below.

2. BIOS Scratch Memory

The last 64 KiB of DRAM bank 1 is BIOS scratch memory. Firmware uses it for its stack and working state, and nothing else reads or writes it.

BIOS scratch region
Start End Size Function
$3F0000 $3FFFFF 64 KiB BIOS scratch memory

The range sits inside DRAM bank 1, so it shares that bank's refresh and initialization rules. Firmware must start DRAM refresh and finish memory initialization before it uses this range.

3. I/O and Firmware Map

The final 2 MiB of the address space is divided into sixteen 128 KiB slots. A slot can contain a device, firmware, or space reserved for later use.

I/O and firmware slots from $E00000 through $FFFFFF
Slot Start End Size Device Purpose and connection
0 $E00000 $E1FFFF 128 KiB MC68901 MFP Provides the UART, timers, interrupt controller, GPIO, and PS/2 keyboard interface. Its 24 canonical registers occupy odd addresses $E00001-$E0002F on the lower data byte.
1 $E20000 $E3FFFF 128 KiB Intel 82077AA-1 Controls two Mitsumi D359M3D drives. Eight canonical host locations occupy odd addresses $E20001-$E2000F on the lower data byte.
2 $E40000 $E5FFFF 128 KiB Yamaha YMF262 OPL3 Provides FM synthesis. Its registers use the lower 8-bit data lane. Four canonical ports occupy $E40001-$E40007.
3 $E60000 $E7FFFF 128 KiB CL-GD5428 VGA I/O registers Provides the host-side interface to the CL-GD5428 registers. VGA I/O port P appears at $E60000 + P. A16 is not decoded, so the 64 KiB port map repeats once in the upper half of the slot. See CL-GD5428 VGA.
4 $E80000 $E9FFFF 128 KiB System control registers Controls the boot ROM overlay and leaves room for future motherboard controls and status registers.
5 $EA0000 $EBFFFF 128 KiB MC6850 MIDI ACIA Provides the MIDI serial interface on the lower 8-bit data lane. Its primary registers are at $EA0001 and $EA0003.
6 $EC0000 $EDFFFF 128 KiB Expansion slot 1 I/O Fixed IO6_n window for front slot 1.
7 $EE0000 $EFFFFF 128 KiB Expansion slot 2 I/O Fixed IO7_n window for front slot 2.
8 $F00000 $F1FFFF 128 KiB DS1285 RTC Provides the real-time clock and battery-backed CMOS RAM. Its 64 canonical byte registers occupy odd addresses $F00001-$F0007F on the lower data byte and repeat every 128 bytes. See DS1285 RTC.
9 $F20000 $F3FFFF 128 KiB Reserved Available for future I/O.
10 $F40000 $F5FFFF 128 KiB Reserved Available for future I/O.
11 $F60000 $F7FFFF 128 KiB Reserved Available for future I/O.
12 $F80000 $F9FFFF 128 KiB Reserved Available for future I/O.
13 $FA0000 $FBFFFF 128 KiB Reserved Available for future I/O.
14 $FC0000 $FDFFFF 128 KiB Reserved Available for future I/O.
15 $FE0000 $FFFFFF 128 KiB Firmware EEPROM The permanent firmware mapping.

4. CL-GD5428 VGA Byte Lanes

The CL-GD5428 expects little-endian byte ordering, while the MC68EC000 uses big-endian byte ordering. The host interface crosses the 16-bit data lanes: CPU D15..D8 connects to CL-GD5428 D7..D0, and CPU D7..D0 connects to CL-GD5428 D15..D8. The corresponding byte-enable connections are swapped with the data lanes.

The byte enables cross with the data. CPU /UDS drives CL-GD5428 SA0 and CPU /LDS drives CL-GD5428 SBHE*, so a byte at CPU address N reaches controller byte address N.

This wiring applies to the CL-GD5428 host-memory window and its I/O-register interface. It does not change either address range in the frozen memory-map specification.

5. Boot ROM Overlay

After a hardware reset, the firmware EEPROM also appears at the bottom of the address space so the CPU can read its reset vectors. Disabling the overlay reveals DRAM bank 0 at those addresses. The EEPROM remains available at its permanent high address throughout this process.

Devices visible in the boot and firmware address ranges
State Start End Visible device
Immediately after hardware reset $000000 $01FFFF Firmware EEPROM alias
After the firmware disables the boot overlay $000000 $01FFFF DRAM bank 0
Always $FE0000 $FFFFFF Firmware EEPROM

The CPU reads its initial stack pointer at $000000 and its initial program counter at $000004, both from the EEPROM alias. The program counter stored in ROM should point into the permanent high mapping, such as $FE0100. The firmware can then disable the low alias without hiding the code it is running.

6. System Control Registers

The system control block uses odd addresses on the lower 8-bit data lane. Only the first two registers have functions.

Motherboard control and status registers in I/O slot 4
Address Register Function
$E80001 SYSREG0 / SYSCTRL Any write disables the boot ROM overlay.
$E80003 SYSREG1 / DEBUG Write-only 8-bit hexadecimal debug display register. The upper and lower nibbles are continuously shown on two internal seven-segment displays.
$E80005 SYSREG2 Reserved.
$E80007 SYSREG3 Reserved.
$E80009 SYSREG4 Reserved.
$E8000B SYSREG5 Reserved.
$E8000D SYSREG6 Reserved.
$E8000F SYSREG7 Reserved.

Lower-byte writes to SYSREG2 through SYSREG7 are acknowledged and ignored. Reads from this block and upper-byte-only accesses end in a bus error.

7. 8-bit Peripheral Addressing

The 8-bit peripherals connect to D7..D0 and use /LDS. As a result, consecutive peripheral registers are two bytes apart in the 68k address space and use odd addresses.

peripheral register N = BASE + 1 + (N * 2)

MC68901 MFP

The MC68901 occupies I/O slot 0 and connects to D7..D0. CPU address lines A1..A5 connect to register selects RS1..RS5. The 24 defined registers run from GPDR at $E00001 through UDR at $E0002F; the complete table is in MC68901 MFP. Because local address lines A16..A6 are not decoded, the 64-byte register block repeats across the slot.

Intel 82077AA-1 Floppy Controller

The 82077AA-1 occupies I/O slot 1 and connects to D7..D0. CPU address lines A1..A3 drive the controller's A0..A2 inputs. Reads and writes to the same address can reach different registers.

82077AA-1 canonical register addresses
Address Read Write
$E20001 Status Register A Undefined
$E20003 Status Register B Undefined
$E20005 Digital Output Register Digital Output Register
$E20007 Tape Drive Register Tape Drive Register
$E20009 Main Status Register Data Rate Select Register
$E2000B FIFO data FIFO data
$E2000D Reserved Reserved
$E2000F Digital Input Register Configuration Control Register

Address lines A16..A4 are not decoded, so this 16-byte register pattern repeats throughout the slot. Firmware uses the first copy shown above. The full circuit and programming rules are in Floppy Controller.

Yamaha YMF262 OPL3

The OPL3 exposes four ports at the start of I/O slot 2. All four accept writes; only port 0 accepts a read.

OPL3 port addresses
Address OPL3 port Read Write
$E40001 Port 0 Timer status Register-array-0 address
$E40003 Port 1 Bus error Register-array-0 data
$E40005 Port 2 Bus error Register-array-1 address
$E40007 Port 3 Bus error Register-array-1 data

CPU A1 and A2 drive YMF262 A0 and A1. The pattern repeats every eight bytes because A16 through A3 are not decoded. Firmware uses the canonical copy above. Upper-byte accesses and reads from ports 1 through 3 end through the motherboard timeout. See YMF262 OPL3 for the complete interface.

MC6850 MIDI ACIA

The MC6850 connects to D7..D0 and uses /LDS. CPU address line A1 drives the ACIA's register-select input, so reads and writes to the same address can access different registers.

MC6850 register addresses and operations
Address Read Write MC6850 RS
$EA0001 Status register Control register 0
$EA0003 Receive data register Transmit data register 1

The MC6850 occupies I/O slot 5. Address lines A16..A2 are not decoded, so the two-register pattern repeats every four bytes throughout the 128 KiB slot. Firmware uses $EA0001 and $EA0003 as the canonical copy. The complete interface is defined in the MC6850 MIDI design.

8. DRAM Organization

Two 2 MiB banks provide 4 MiB of system DRAM. Each bank uses four 1M x 4 devices to form the computer's 16-bit data width.

Physical DRAM banks
Bank Address range DRAM devices Width Capacity
0 $000000-$1FFFFF 4 x TMS44400DJ-70 (1M x 4) 16-bit 2 MiB
1 $200000-$3FFFFF 4 x TMS44400DJ-70 (1M x 4) 16-bit 2 MiB
Total system DRAM 4 MiB