DS1285 RTC

1. Purpose and Scope

The DS1285 supplies the battery-backed clock, calendar, alarm, periodic interrupt, update-ended interrupt, and 50 bytes of CMOS RAM. This page fixes every motherboard connection to the device and the discrete adapter that converts the MC68EC000 bus into the DS1285's multiplexed address/data cycle.

The Memory Map owns the slot assignment. Bus and Address Decode owns IO8_n, the global completion tree, and timeout behavior. The MFP owns the GPIP vector, Clock and Reset owns PERIPH_RESET_n, and the DRAM clock buffer supplies INT_CLK.

Signal names ending in _n, and signal names written with a leading slash, are active low. The board uses +5 V logic and through-hole packages. Every IC family selected here existed before 1994.

2. Architecture

MC68EC000 bus                         DS1285 RTC

A6..A1 ----> U_RTC_ADDR ------------> AD5..AD0   address phase
GND -------> U_RTC_ADDR ------------> AD7..AD6
D7..D0 <--> U_RTC_DATA <-----------> AD7..AD0   data phase
R/W -------> U_RTC_INV -------------> transceiver direction
R/W --------------------------------> R/W
IO8_n ------------------------------> /CS
LDS_n -----> U_RTC_REQ ------------> RTC_CYCLE
INT_CLK ---> U_RTC_INV --> RTC_CLK
RTC_CYCLE -> U_RTC_SYNC --> U_RTC_SEQ
U_RTC_SEQ + FAST gates ------------> AS, DS, RTC_DTACK_n
PERIPH_RESET_n ---------------------> /RESET

32.768 kHz crystal -----------------> X1, X2
CR2032 + ---------------------------> VBAT
/IRQ ------- 4.7 kohm pull-up ------> MC68901 GPIP3

The DS1285 uses Motorola timing with MOT tied to +5 V. Its AS and DS inputs are active-high pulses; they are local signals and are not the processor's active-low strobes. The adapter presents the register address first, then turns the shared RTC pins around for data.

3. Bus Interface

Cycle Qualification

U_RTC_REQ is one SN74F02 gate. It asserts RTC_CYCLE only while slot 8 and the lower byte lane are both selected.

RTC_CYCLE = NOT (IO8_n OR LDS_n)

An upper-byte-only access leaves RTC_CYCLE low and reaches the motherboard bus timeout. A word access includes the lower lane and completes, but only D7..D0 contain valid RTC data. Software shall use byte accesses at odd addresses.

Address and Data Paths

U_RTC_ADDR is an SN74HCT244N. Six channels connect A1..A6 to AD0..AD5; its remaining inputs are grounded and drive AD6 and AD7 low during the address phase. Both enables share RTC_ADDR_OE_n.

U_RTC_DATA is an SN74HCT245N. Its A-side connects to CPU D7..D0 and its B-side connects to RTC AD7..AD0. RTC_DATA_OE_n keeps it disabled during the address phase. U_RTC_INV drives DIR high for a CPU-to-RTC write and low for an RTC-to-CPU read.

RTC_DATA_DIR = NOT R/W

R/W = 0: U_RTC_DATA A -> B, CPU writes DS1285
R/W = 1: U_RTC_DATA B -> A, CPU reads DS1285

4. Adapter Sequence

U_RTC_SYNC is an SN74HCT74N. Its first flip-flop samples a high level after RTC_CYCLE begins, and its second flip-flop produces RTC_REQ_SYNC. The raw cycle signal asynchronously clears both stages when the CPU releases the access. This keeps an asynchronous request from driving the timing chain directly.

U_RTC_SEQ is a CD74HCT164E shift register. Its serial inputs are tied to RTC_REQ_SYNC, its active-low clear connects to RTC_CYCLE, and it advances on rising edges of RTC_CLK. Outputs QA through QF define the transaction.

The QC-only dead interval gives break-before-make control between U_RTC_ADDR and U_RTC_DATA. QE supplies one full wait state after DS rises; QF acknowledges after two 100 ns read-data intervals.

Control Equations

RTC_AS            = QA AND NOT QB
RTC_ADDR_OE_n     = NOT (RTC_CYCLE AND NOT QC)
RTC_DATA_OE_n     = NOT (RTC_CYCLE AND QD)
RTC_DS            = RTC_CYCLE AND QD
RTC_DTACK_n       = NOT (RTC_CYCLE AND QF)

U_RTC_NAND and U_RTC_AND implement these equations. U_RTC_INV supplies the inverted QB and QC terms. The raw RTC_CYCLE term forces DS low, disables both bus drivers, clears the sequence, and releases RTC_DTACK_n as soon as either IO8_n or LDS_n rises.

5. Register Map

CPU A1..A6 become DS1285 address bits 0 through 5. The canonical address of RTC location n is $F00001 + 2n. Address lines A16..A7 do not enter the local decode, so the 128-byte block repeats throughout slot 8.

Control Registers

Register A, $0A:  UIP DV2 DV1 DV0 RS3 RS2 RS1 RS0
Register B, $0B:  SET PIE AIE UIE SQWE DM 24/12 DSE
Register C, $0C:  IRQF PF AF UF 0 0 0 0
Register D, $0D:  VRT 0 0 0 0 0 0 0

DV2..DV0 = 010 selects the 32.768 kHz time base and lets the divider run. DM selects binary or BCD time fields, and 24/12 selects the hour format. PIE, AIE, and UIE enable the periodic, alarm, and update-ended interrupt sources. Register C reports those sources and clears all asserted flag bits when read.

The DS1285 has no century register. System software must combine its two-digit year with a separately maintained century policy.

6. Clock and Battery

32.768 kHz Crystal

Y_RTC is a 32.768 kHz tuning-fork crystal connected directly between pins 2 and 3. The specified part is the IQD Frequency Products LFXTAL014219B. Any substitute must be a parallel-resonant crystal specified for 6 pF load capacitance and no more than 50 kohms series resistance. The RTC supplies its own bias and load network, so no external crystal capacitors or feedback resistor are fitted.

Register A must contain DV2..DV0 = 010 before the divider counts time. Firmware shall verify that seconds advance before accepting the stored time.

Backup Cell

BT_RTC is a replaceable CR2032 primary lithium cell in a through-hole holder. Its positive terminal connects directly to VBAT; its negative terminal connects to ground. No series diode, resistor, or charging circuit is permitted in the battery path.

The recommended holder is the MPD BA2032. It is a through-hole retainer for a 20 mm cell. Any through-hole holder is acceptable.

The DS1285 disconnects the host interface during power failure and runs the oscillator and CMOS RAM from VBAT. Register D bit VRT reports whether the retained time and RAM can be trusted. Firmware shall treat a cleared VRT as loss of clock state.

7. Reset Behavior

DS1285 /RESET connects directly to PERIPH_RESET_n. The 250 ms minimum motherboard power-on reset exceeds the RTC's 200 ms power-up requirement. A processor RESET instruction holds PERIPH_RESET_n low for about 12.4 us, above the RTC's 5 us minimum reset pulse width.

Reset clears the three interrupt-enable bits, the interrupt flags, IRQF, and SQWE. It releases /IRQ and blocks host accesses while asserted. Reset does not change the clock, calendar, alarms, general-purpose RAM, SET, DM, 24/12, or DSE.

U_RTC_SYNC and U_RTC_SEQ clear whenever no qualified RTC cycle is active. They need no motherboard reset connection and cannot hold RTC_DTACK_n low across reset.

8. Interrupts

The DS1285 open-drain /IRQ output connects to MC68901 GPIP3. R_RTC_IRQ is a 4.7 kohm pull-up from that net to +5 V. The MFP detects the falling edge and supplies vector $43 during the processor's level-6 interrupt acknowledge. See Interrupts and MFP GPIP Assignment.

Any enabled flag asserts /IRQ and sets IRQF. The output remains low until software reads Register C or reset clears the condition. The interrupt handler shall read Register C once, retain the returned byte, and service every set flag; that read clears all flags present at the start of the access.

9. Firmware Access Rules

1. Use byte instructions at odd canonical addresses.
2. On startup, read Register D and reject retained state if VRT is zero.
3. Program Register A with DV2..DV0 = 010.
4. Set SET before changing time, calendar, alarm, data mode, or hour format; clear it after writing all related fields.
5. Leave DSE clear. Its April and October rule does not match current daylight-saving rules.
6. For a coherent read, poll UIP until zero, then read the time and calendar fields within the guaranteed 244 us window.
7. Configure GPIP3 for a falling edge before enabling an RTC source. Read Register C to discard stale flags first.
8. After power-up or battery replacement, confirm that the seconds register advances before marking the clock valid.

10. Package and Pin Map

DS1285

Adapter Packages

Each adapter package connects to +5 V and ground. No logic input is left open.

11. Timing and Electrical Checks

RTC Access Timing

The two synchronizer stages add one to two 100 ns periods before RTC_REQ_SYNC rises. Synchronizer latency changes total bus-cycle length, but not the timing between RTC strobes.

A request completes about 700 to 800 ns after qualification, depending on its clock phase. This is inside the motherboard's 51.1 us timeout.

Acknowledgement Release

When LDS_n or IO8_n rises, U_RTC_REQ clears RTC_CYCLE. U_RTC_NAND then releases RTC_DTACK_n without waiting for a clock edge.

U_RTC_REQ SN74F02, tPHL     5.3 ns maximum
U_RTC_NAND SN74F00, tPLH    6.0 ns maximum
group SN74F21, tPLH         5.3 ns maximum
final SN74F21, tPLH         5.3 ns maximum
SN74F32 timeout mask, tPLH  6.6 ns maximum
------------------------------------------------
component total            28.5 ns
MC68EC000 limit           110.0 ns
board allowance            81.5 ns

The strobe rise drives RTC_CYCLE low through the F02 NOR (tPHL) and then drives RTC_DTACK_n high through the F00 NAND (tPLH). Every later stage is also a rising edge.

Logic Levels and Loading

The HCT bus parts accept the MC68EC000's TTL levels and keep static loading low. FAST control outputs meet the DS1285's TTL thresholds. Every adapter IC has a 100 nF ceramic bypass capacitor; U_RTC also has a 1 uF local bulk capacitor.

12. Parts Added

The DS1285, CD74HCT164, SN74HCT244, SN74HCT245, SN74HCT74, and 74F gate families were documented before 1994. The adapter adds eight 100 nF ceramic bypass capacitors and one 1 uF capacitor beside U_RTC.

13. Board Layout

• Place Y_RTC beside pins 2 and 3. Keep its traces short and inside a quiet ground surround. Do not route clocks, bus signals, or battery-current paths beneath the crystal or the upper-left quarter of U_RTC.
• Put BT_RTC where its cell can be replaced without removing another board. Mark polarity on copper and silkscreen.
• Keep AD7..AD0 short among U_RTC, U_RTC_ADDR, and U_RTC_DATA.
• Route RTC_CYCLE directly to the asynchronous clear pins and U_RTC_NAND. Avoid stubs on RTC_CLK, RTC_AS, RTC_DS, and RTC_DTACK_n.
• Place each 100 nF capacitor at its IC supply pins and the 1 uF capacitor beside U_RTC pins 24 and 12.
• After routing, include the two bus buffers in the CPU address and data capacitance totals in Bus and Address Decode.
• Include the U_RTC_INV clock input and routed branch in the INT_CLK load. The total at U_DRAM_CLK_BUF pin 3 must not exceed the 50 pF timing load.
• Measure the routed RTC_DTACK_n release path and keep its board contribution below 81.5 ns.
• Measure RTC_AS, RTC_DS, and RTC_CLK at U_RTC. Preserve the timing-table margins across supply and temperature.
• With +5 V removed, verify 2.5 V to 4.0 V at VBAT and check that the coin cell does not feed a motherboard rail.

14. Internal Signal Reference

15. Sources

• Dallas Semiconductor, DS1285/DS1285Q Real Time Clock. Device selection, organization, features, and pinout.
• Motorola, MC146818A Real-Time Clock Plus RAM. Register definitions, programming model, interrupts, and multiplexed-bus timing.
• Maxim Integrated, DS12885/DS12887 Real-Time Clocks. Electrical, timing, oscillator, battery, reset, and layout limits for the DS1285 replacement family.
• Texas Instruments, CD54/74HC/HCT164 Shift Registers. Sequencer function, pinout, and timing.
• Texas Instruments, SN74HCT244, SN74HCT245, and SN74HCT74 data sheets. Address driver, data transceiver, and synchronizer.
• Texas Instruments, SN74F00, SN74F02, SN74F04, and SN74F08 data sheets. Qualification, strobes, enables, clock buffering, and acknowledgement.