Expansion Slots

1. Purpose and Scope

The computer accepts two removable cards from the front of the enclosure. Guide rails carry each card to a DIN 41612 connector at the rear. Power must be off before a card is inserted or removed.

Each physical slot has one fixed 2 MiB memory window and one fixed 128 KiB I/O window. Moving a card between slots changes its addresses without jumpers or configuration storage. A card may use either or both windows, but it must not decode outside them.

The motherboard buffers every outgoing signal and gives each slot its own data transceivers. Cards cannot request the bus, become bus master, or perform DMA. An empty or nonresponding slot produces a bus error through the existing 51.1 microsecond minimum timeout.

2. Address Assignment

The connectors call these pins MEM_SEL_n and IO_SEL_n. Card schematics can use one connector symbol in either slot. A card that decodes fewer local address bits mirrors its registers or memory within its assigned window.

EXP_MEM5_n, EXP_MEM6_n, and IO9_n..IO14_n remain reserved motherboard decode outputs. They do not reach either connector, and accesses to their unimplemented ranges time out under memory-map revision 1.0.

3. Mechanical Interface

Each card uses a 100 mm by 160 mm, 1.6 mm thick PCB with a 96-contact right-angle male DIN 41612 connector on its rear edge. A 3U front panel, approximately 128.4 mm high and 30.48 mm wide, gives each card a 6 HP bay. Both bays need about 61 mm of chassis width.

The 6 HP pitch permits a 20 mm component envelope on the component side and a 4 mm lead-and-solder envelope on the other side. Printed upper and lower guide channels support the card edges. Print the guides in PETG, ABS, or nylon rather than PLA.

Each front panel uses a printed pull handle and two cam ejectors on M3 pivots. The cams bear on reinforced chassis ledges, seat the connector evenly, and break it free before the user pulls the handle. Captive M3 thumbscrews at the top and bottom retain the seated card. The cams shall provide at least 3:1 mechanical advantage over their first 3 mm of travel.

The pair is specified for at least 500 mating cycles and up to 90 N insertion force. Use side-coding hardware so an expansion card cannot enter another DIN bay. Both expansion slots use the same key. The guides shall prevent one-row or one-position offset mating.

4. Architecture

address/control --+-- slot 1 HCT244 banks --> J_EXP1
                  +-- slot 2 HCT244 banks --> J_EXP2

CPU D15..D0 <--> slot 1 HCT245 pair <--> J_EXP1
             +--> slot 2 HCT245 pair <--> J_EXP2

J_EXP1 CARD_DTACK_n --+
                       +-- FAST AND --> EXP_DTACK_n --> completion tree
J_EXP2 CARD_DTACK_n --+

J_EXP1 EXP_IRQ_n -----+
                       +-- wired-OR --> level-3 interrupt
J_EXP2 EXP_IRQ_n -----+

Separate drivers remove one card's connector and trace capacitance from the other card's signal path. The processor-side ports of the data transceivers share D15..D0, but fixed nonoverlapping selects enable only one slot. A card must still qualify every data driver and completion output with its connector select.

5. Signal Rules

Bus logic uses +5 V TTL-compatible levels. Cards shall accept VIL <= 0.8 V and VIH >= 2.0 V and deliver VOL <= 0.4 V at the specified open-collector sink current. +12 V is power only and shall not touch a bus signal.

6. Connector Pinout

This is the mating-interface view, not a solder-side view. Connector drawings can reverse the visible order. Verify row letters, position numbers, and pin-1 marks on both footprints before PCB release.

Row b is ground at every position. Six contacts carry +5 V, four carry +12 V, and 37 carry ground. Parallel every contact assigned to the same rail on both boards.

7. Address and Control Buffers

Each slot uses four SN74HCT244N packages. Three carry A23..A1; the fourth carries the strobes, direction, selects, clock, and reset. Both output-enable pins on every package are grounded. No card pin connects to a processor output or an unbuffered motherboard select.

Put a 33 ohm series resistor between every HCT244 output and its connector contact. These 31 resistors per slot provide source damping and limit current during accidental contention.

8. Data Bus

Two SN74HCT245N packages serve each slot. Their A ports face the card and their B ports face the CPU. Both DIR inputs connect directly to motherboard R_W. A high read level selects A-to-B; a low write level selects B-to-A.

EXP1_CYCLE_n = EXP_MEM2_n AND IO6_n
EXP2_CYCLE_n = EXP_MEM3_n AND IO7_n

R_W = 1: card A port --> CPU B port
R_W = 0: CPU B port  --> card A port

Gates 1 and 2 of U_EXP_GLUE, an SN74F08N, generate the active-low enables. Each enable drives both transceivers for its slot. R_W is valid before the qualified select, so direction is established before output enable. The motherboard passes all 16 bits when selected; the card qualifies its own byte lanes.

Lower-lane 8-bit cards connect to D7..D0, respond to LDS_n, and place canonical registers at odd addresses. Upper-lane cards use D15..D8, UDS_n, and even addresses.

9. Cycle Completion

Each connector has a separate CARD_DTACK_n net and a motherboard 1 kohm, 5 percent pull-up. Cards use an open-collector or open-drain output and never drive high. Gate 3 of U_EXP_GLUE combines the inputs:

EXP_DTACK_n = EXP1_CARD_DTACK_n AND EXP2_CARD_DTACK_n

The push-pull result enters U_DTACK_B gate 1 in the shared completion tree. A card may assert completion only while its select and a supported byte strobe are active. For reads, requested data must already be valid. For writes, the card must have accepted or be ready to accept the data.

Release completion as soon as the select or all supported strobes negate. A card that cannot finish within 50 microseconds leaves the line high and lets the motherboard timeout produce a bus error. Every completion output shall sink at least 8 mA at 0.4 V. One SN74LS07N channel meets this rule.

10. Interrupts

Both connectors share EXP_IRQ_n. The existing 4.7 kohm motherboard pull-up holds it high; either card can pull it low. It enters the priority encoder at level 3 and receives autovector 27, whose exception-vector address is $00006C.

A card keeps its request low until its driver clears every enabled cause. The level-3 handler polls both installed drivers and repeats while the line remains low. Interrupt assertion gives no permission to drive data or completion; the motherboard terminates the acknowledge with /AVEC.

11. Clock and Reset

Gate 1 of U_EXP_CLK_PHASE, an SN74F04N, reads the complementary 10 MHz divider output at U_CPU_CLK pin 8. It produces EXP_CLK_ROOT, a nominally in-phase copy of CPU_CLK_10. The per-slot control HCT244s drive separate connector clocks from that root.

Pin 8 continues to drive pin 12 for toggle feedback. Include the F04 input in the divider feedback waveform check. Cards may use the connector clock for state machines and baud-rate division, but shall not assume specified edge skew from the CPU clock. A card-side buffer is required for more than two clock loads.

PERIPH_RESET_n asserts for power-on reset, manual reset, and the CPU RESET instruction. A card with active-high reset inverts it locally. A device without reset shall keep bus outputs disabled until its software initialization is complete.

12. Power Distribution

Each slot has separate protection. An RXEF250 radial resettable fuse feeds +5 V, and an RXEF110 feeds +12 V. Cards may draw no more than 1.0 A continuously from +5 V and 0.4 A from +12 V. Reduce those limits if measured fuse or enclosure temperature requires it.

The system supply shall cover the motherboard plus 2.0 A on +5 V and 0.8 A on +12 V with both slots full. A card shall not feed current back into either rail. Put at least 47 uF on card +5 V, 10 uF on card +12 V, and 100 nF at every IC. Do not exceed 1000 uF per card rail without checking supply startup and fuse behavior again.

The connector has no make-first sequence. Label the front panel POWER OFF BEFORE REMOVING CARD. Software shutdown does not make live insertion or removal safe.

13. Card Requirements

Cards may use TTL, LS, F, HC, HCT, ACT, or another period-correct 5 V family when the complete interface meets these limits. Plain HC inputs are not suitable for motherboard signals guaranteed high at only 2.0 V. HCT inputs are the default.

Protect external ports against cable discharge and out-of-range voltage at the front panel. Do not return cable-shield current through a bus ground contact when the enclosure provides chassis ground.

14. Software Contract

The bus has no enumeration register. System configuration identifies the card and driver in each physical slot. Probing an empty slot causes a bus error, so discovery code needs a temporary bus-error handler or saved configuration.

Drivers use byte operations for 8-bit registers unless a card defines the unused word byte. The shared level-3 handler polls both card drivers, clears every reported cause, and polls again if EXP_IRQ_n stays low.

15. Example 8-Bit Register Card

This lower-byte read/write latch tests either slot. It responds throughout the slot's I/O window, so its canonical register is $EC0001 in slot 1 or $EE0001 in slot 2. It ignores MEM_SEL_n and does not request interrupts.

D7..D0 --> HCT574 register --> HCT244 read driver --> D7..D0

IO_SEL_n + LDS_n + R_W  --> write strobe --> HCT574 CLK
IO_SEL_n + LDS_n + /R_W --> read enable  --> HCT244 OE_n
IO_SEL_n + LDS_n -------> three-stage HCT74 delay
                                  |
                                  +--> HCT04 --> LS07 --> CARD_DTACK_n

Logic equations

NOT_R_W      = NOT R_W
EX_WRITE_n   = IO_SEL_n OR LDS_n OR R_W
EX_READ_n    = IO_SEL_n OR LDS_n OR NOT_R_W
EX_ACCESS_n  = IO_SEL_n OR LDS_n
EX_ACCESS    = NOT EX_ACCESS_n
EX_ACK_CLR_n = EX_ACCESS AND PERIPH_RESET_n

stage 1 D = 1; stage 2 D = stage 1 Q; stage 3 D = stage 2 Q
all stage clocks = EXP_CLK_10; all CLR_n inputs = EX_ACK_CLR_n
all PRE_n inputs = 1
CARD_DTACK_n = open-collector copy of stage 3 /Q

U_EX_REG clocks on the rising edge of EX_WRITE_n when the selected write ends. Its data has been stable throughout the write strobe. U_EX_READ drives only while the I/O select, lower strobe, and read direction are active.

Three flip-flops in U_EX_ACK_A and U_EX_ACK_B, both SN74HCT74N packages, shift a one down the chain. Their asynchronous clear stays low while unselected or reset. The third stage allows at least two full 10 MHz periods for read data before its complementary output pulls completion low. Select release clears the chain and releases completion without waiting for a clock.

Ground unused logic inputs and leave their outputs open. Fit 100 nF at every IC and 47 uF across card +5 V and ground. The example does not use +12 V.

Example-card package connections

On U_EX_OR, pins 1 and 2 receive IO_SEL_n and LDS_n; pin 3 is EX_ACCESS_n. Pins 4 and 5 receive EX_ACCESS_n and R_W; pin 6 is EX_WRITE_n. Pins 9 and 10 receive EX_ACCESS_n and NOT_R_W; pin 8 is EX_READ_n. Ground pins 12 and 13 and leave pin 11 open.

U_EX_INV uses pins 1 to 2 for R_W to NOT_R_W and pins 3 to 4 for EX_ACCESS_n to EX_ACCESS. U_EX_AND uses pins 1 and 2 for EX_ACCESS and PERIPH_RESET_n; pin 3 is EX_ACK_CLR_n. Ground every remaining input on both packages.

U_EX_REG pin 1 is grounded, pin 11 receives EX_WRITE_n, pins 19 through 12 receive connector D0..D7, and pins 2 through 9 produce REG0..REG7. Connect those register outputs to U_EX_READ in the common HCT244 channel order from section 16. Its two output-enable pins receive EX_READ_n, and its outputs drive connector D0..D7.

16. Motherboard Package and Pin Map

References ending in 1 belong to slot 1; references ending in 2 belong to slot 2. The mappings are otherwise identical.

Pins 1 and 19 are grounded, pin 20 is +5 V, and pin 10 is ground. Assign channels in ascending order to each package's signal list in section 7. References are U_EXP_ADDR_LO1, U_EXP_ADDR_MID1, U_EXP_ADDR_HI1, U_EXP_CTRL1, and the matching slot-2 names.

Give every logic package 100 nF and 1 uF between its supply pins. Put the 100 nF part beside the package.

17. Timing and Electrical Checks

Outgoing and data paths

At 4.5 V and 50 pF, the SN74HCT244 has 42 ns maximum propagation delay over the chosen temperature range. The card's 20 pF limit leaves 30 pF for connector, resistor, trace, socket, and probe. Under the same conditions, the commercial SN74HCT245 has 28 ns maximum data delay and 58 ns maximum enable time. A card includes that delay and places read data before it asserts completion.

Completion assertion

Assertion is a falling edge at every node, so each stage uses its high-to-low maximum.

U_EXP_GLUE F08, tPHL                 6.3 ns
two F21 completion levels, tPHL     11.0 ns
F32 timeout mask, tPHL               6.3 ns
component subtotal                  23.6 ns

This excludes card, connector, and trace delay. A synchronous card asserts after its data is stable and holds both through the processor's terminating edge.

Completion release

With 50 pF card load, another 50 pF for the connector path and probe, a 1.05 kohm maximum pull-up, and a 4.75 V rail, an ideal RC node reaches the FAST 2.0 V threshold in 57.4 ns:

t = -1050 ohms * 100 pF * ln(1 - 2.0 / 4.75) = 57.4 ns

Release is a rising edge at every node, so each stage uses its low-to-high maximum: 6.6 ns through the F08, 10.6 ns through two F21 levels, and 6.6 ns through the F32. The 81.2 ns total leaves 28.8 ns for board delay against the CPU's 110 ns completion-release limit. If measurement misses the limit, reduce capacitance or lower the pull-up after checking card sink current.

RC to the 2.0 V FAST threshold      57.4 ns
U_EXP_GLUE F08, tPLH                 6.6 ns
two F21 completion levels, tPLH     10.6 ns
F32 timeout mask, tPLH               6.6 ns
------------------------------------------------
component total                     81.2 ns
MC68EC000 limit                    110.0 ns
board allowance                     28.8 ns

DC levels

Two slot-buffer inputs add at most 2 uA DC load to each CPU signal. At 4.5 V, an HCT244 guarantees at least 3.84 V while sourcing 6 mA and no more than 0.33 V while sinking 6 mA. Margins to the card's 2.0 V and 0.8 V thresholds are 1.84 V high and 0.47 V low before interconnect drop.

18. Parts Added

Every listed IC design predates 1994. HCT logic was established in the 1980s; the HCT245 and HCT574 documents date their designs to 1984, HCT32 to 1988, and LS07 to no later than 1990. The FAST family appears in the 1980 Fairchild data book. Later datasheet revisions do not change the period rule.

19. Board Layout

• Place each slot's buffers behind its connector and every 33 ohm resistor at its driver.
• Join row-b contacts to a ground plane with short vias; use wide pours for power and ground.
• Record routed completion capacitance and delay, then repeat the 110 ns release check with a probe.
• Model guides, ejectors, reaction ledges, captive fasteners, and connector alignment before fixing motherboard holes.

20. Assembled-System Acceptance

21. Internal Signal Reference

22. Sources

• Motorola, M68000 User's Manual, bus cycles, byte strobes, timing, reset, and interrupts.
• Texas Instruments, SN74HCT244 and SN74HCT245, buffering and transceiver limits.
• Texas Instruments, SN74F08, SN74F04, and SN74LS07, glue and open-collector timing.
• Texas Instruments, SN74HCT32, SN74HCT08, SN74HCT04, SN74HCT574, and SN74HCT74, example-card logic.
• HARTING, DIN-Signal C096MS-3,0C1-1 and the DIN 41612 Type C catalog.
• Littelfuse, RXEF Series Radial Leaded PPTC Datasheet, current ratings and temperature derating.
• The project Memory Map, Bus and Address Decode, Interrupts, and Clock and Reset documents define the matching interfaces.