1. Access Rules
The block responds to IO4_n qualified by
LDS_n, so every register sits at an odd address on the
lower data byte. U_SYSREG decodes CPU address lines
A3..A1 into eight register selects and ignores
A16..A4, so the eight registers repeat every 16 bytes
through the 128 KiB slot. Software uses the canonical addresses
$E80001 through $E8000F.
A lower-byte write to any of the eight registers is acknowledged.
Writes to SYSREG2 through SYSREG7 are
acknowledged and ignored. Reads from this block and upper-byte-only
accesses are not acknowledged and end in a bus error at the timeout.
The bus and address decode document
gives the decoder connections and the
SYSREG_DTACK_n equations.
2. Registers
| Address | Register | Function |
|---|---|---|
$E80001 |
SYSREG0 / SYSCTRL | Any write disables the boot ROM overlay. |
$E80003 |
SYSREG1 / DEBUG | Write-only 8-bit hexadecimal debug display register. The upper and lower nibbles are continuously shown on two internal seven-segment displays. |
$E80005 |
SYSREG2 | Reserved. |
$E80007 |
SYSREG3 | Reserved. |
$E80009 |
SYSREG4 | Reserved. |
$E8000B |
SYSREG5 | Reserved. |
$E8000D |
SYSREG6 | Reserved. |
$E8000F |
SYSREG7 | Reserved. |
The frozen register map is in the memory map. The reserved registers leave room for later motherboard controls and status without a new I/O slot.
3. Boot Overlay Control
After reset the firmware EEPROM also appears at the bottom of the
address space so the CPU can fetch its reset vectors. A write to
SYSREG0 / SYSCTRL removes that alias and reveals DRAM
bank 0. The written value is ignored.
The decoded write is qualified into an active-low pulse.
OVERLAY_WRITE_n = SYSREG0_n OR R/W
U_OVERLAY, an SN74HCT74N, holds the overlay
state on its asynchronous inputs. RESET_n drives the
preset and enables the overlay; OVERLAY_WRITE_n drives
the clear and disables it. The register is one-way. Software cannot
restore the overlay, and only a board reset sets it again. The
boot-overlay reset checks
cover a reset that arrives during an overlay-clear write.
The memory map lists the addresses this write affects, and the firmware ROM document describes the bring-up sequence that ends with it.
4. Debug Register
A write to SYSREG1 / DEBUG stores D7..D0 in
U_DEBUG, an SN74HCT574N with its output
enable tied low. The decoded write is qualified and then inverted to
make the clock edge.
DEBUG_WRITE_n = SYSREG1_n OR R/W
DEBUG_CLK = NOT DEBUG_WRITE_n
A spare SN74HCT04 gate produces DEBUG_CLK,
so U_DEBUG captures on the leading edge of the qualified
write while the CPU still drives the data bus. The stored byte leaves
on DEBUG_Q7..DEBUG_Q0. Its two nibbles feed the
debug display circuit, which converts
each to a hexadecimal digit. The register is write-only; a read ends
in a bus error like the rest of the block.