68EC000 Computer

This site collects the design documents and datasheets for the 68EC000 computer. Each page records its revision and design status. Board layout and measurements on the assembled machine remain to be done. Schematics and PCB files are not published yet.

Claude and Codex were used to help format and put my ideas into the design documents.

CPU
MC68EC000FN10
Address space
16 MiB
Data bus
16-bit
Main RAM
4 MiB of TMS44400 FPM DRAM
Firmware
128 KiB in four AT28C256-15PU EEPROMs, always read-only
Video controller
CL-GD5428 VGA controller with its 16-bit byte lanes swapped for the MC68EC000's big-endian bus and 2 MiB of video RAM
Floppy controller
Intel 82077AA-1 using interrupt-driven programmed I/O
Floppy drives
Two Mitsumi D359M3D 3.5-inch, 1.44 MB drives on one twisted cable
Sound
Yamaha YMF262 OPL3, two YAC512 converters, stereo headphone amplifier, volume control, and 3.5 mm output

Design Documents

Project documents
Document Status Contents
Memory Map Revision 1.1; address specification frozen Address ranges, I/O slots, boot overlay, peripheral registers, and DRAM organization.
Bus and Address Decode Revision 1.0 pre-layout design Bus cycles, address decoders, boot-overlay logic, worked decode examples, timing, and bus termination.
Clock and Reset Revision 1.0 pre-layout design 10 MHz clock and active-low reset generation.
Power Control Revision 1.0 pre-layout design Front-panel power-button timing, power-state logic, relay drive, and switched +5 V and +12 V rails.
Interrupts Revision 1.0 pre-layout design Priority encoding, acknowledge decode, autovector and MFP vectors, and spurious-interrupt handling.
System Control Revision 1.0 Boot-overlay and debug-register behavior.
Debug Display Revision 1.0 pre-layout design Two-digit hexadecimal seven-segment display.
DRAM Revision 1.0 pre-layout design DRAM organization, discrete controller, refresh, initialization, timing, electrical checks, and assembled-board acceptance.
Firmware ROM Revision 1.0 pre-layout design AT28C256 organization, read-only wiring, and completion timing.
MC68901 MFP Revision 1.0 pre-layout design Bus interface, register map, timers, interrupt routing, bidirectional PS/2 keyboard, and MAX232 RS-232 port.
Floppy Controller Revision 1.0 pre-layout design Intel 82077AA-1 bus adapter, programmed-I/O interface, and two Mitsumi D359M3D drives.
CL-GD5428 VGA Revision 1.0 pre-layout design ISA-mode bus adapter, swapped byte lanes, linear 2 MiB aperture, display memory, configuration EEPROM, dedicated clock, and DE-15 output.
YMF262 OPL3 Revision 1.0 pre-layout design FM-synthesis bus adapter, dedicated clock, reset, two YAC512 converters, stereo mixing, volume control, and headphone output.
MC6850 MIDI Revision 1.0 pre-layout design MC6850 bus adapter, register map, clocking, interrupts, and isolated MIDI IN, OUT, and hardware THRU.
DS1285 RTC Revision 1.0 pre-layout design Multiplexed-bus adapter, register map, timing, crystal, battery, reset, firmware access rules, and interrupt wiring.
Expansion Slots Revision 1.0 pre-layout design Two front-loading DIN 41612 slots, fixed address windows, buffered bus interface, pinout, power, card rules, and example card.

Datasheets

Component documentation used by the design
Document Link Used for
MC68000 User Manual PDF CPU architecture, bus cycles, function codes, and interrupts.
MC68000 User Manual Addendum PDF Corrections to the MC68000 user manual.
Intel 82077AA-1 PDF Floppy controller, FIFO, host timing, and drive interface.
Mitsumi D359M3D PDF Two 3.5-inch drives; capacity, data rate, power, and mechanical specifications.
Microchip AT28C256 PDF 32K x 8 firmware EEPROM; four AT28C256-15PU devices are used.
Microchip ATF16V8BQL PDF Static hexadecimal seven-segment decoder for the debug display; two ATF16V8BQL-15PU devices are used.
Kingbright SA56-11EWA PDF 0.56 inch red common-anode seven-segment display; two are used by the debug display.
Cirrus Logic CL-GD542X Data Book PDF CL-GD5428 pinout, ISA host timing, configuration straps, and the VGA register port map. Its little-endian byte lanes are swapped at the MC68EC000 bus.
Cirrus Logic CL-GD542X Technical Reference Manual PDF CL-GD5428 extension registers, display-memory configurations, MCLK and DRAM timing, EEPROM interface, and reference-design circuits.
Dallas DS1285 PDF Real-time clock and battery-backed CMOS RAM.
Motorola MC146818A PDF RTC register and programming reference.
Motorola MC6850 PDF MIDI ACIA.
6N138 PDF Isolated MIDI input receiver.
SN74LS390 PDF MIDI 5 MHz to 500 kHz clock divider.
Motorola MC68901 PDF USART, timers, interrupt controller, and GPIO.
Maxim MAX232 PDF RS-232 voltage-level conversion for the MFP USART.
Texas Instruments TMS44400 PDF 1M x 4-bit FPM DRAM.
Yamaha YMF262 PDF OPL3 FM synthesizer, bus timing, and four-channel output.
Yamaha YAC512 PDF Two-channel converter used twice by the OPL3 audio circuit.
LT1054 PDF Negative supply for the OPL3 converter buffers.
CD74HCT123 PDF Local YMF262 reset stretcher.
TL431 PDF Shunt reference for the CL-GD5428 DAC current sink.
NJM4556A PDF Dual high-current OPL3 headphone amplifier; the installed part is the NJM4556AD.
HARTING DIN 41612 Type C PDF Two 96-contact front expansion-slot connectors.
Littelfuse RXEF Series PDF Resettable +5 V and +12 V expansion-slot fuses.
CD74HCT21 PDF Dual four-input AND gates for the interrupt-acknowledge type field, the unwired-level decode, and the firmware ROM byte select.
CD74HCT4040 PDF Bus-timeout, DRAM startup, and refresh counters.
CD74ACT157 PDF DRAM row/column address multiplexers.
CD74ACT244 PDF DRAM clock, reset, and control-net buffers.
SN74F00 / F02 / F04 / F08 / F20 / F30 / F32 / F86 F00, F02, F04, F08, F20, F30, F32, F86 FAST glue logic used by the DRAM controller and by the floppy, RTC, MIDI, OPL3, VGA, and expansion adapters. The F32 also carries the final DTACK_n timeout mask.
SN74F10 / F21 / F138 / F161A / F175 F10, F21, F138, F161A, F175 DRAM timing, decode, state, and initialization logic. Two F21 packages form the motherboard completion-response tree, and the F10 qualifies the DRAM acknowledgement with the raw bus strobes.
Philips N74F194 PDF DRAM transaction register.
Fairchild FAST Data Book (1980) PDF Historical source for the 74F191PC refresh-credit counter.
SN74HCT04 PDF Logic NOT gates.
SN74HCT08 PDF CPU-space detection and firmware ROM selection.
SN74HCT244 PDF Normal-cycle distribution, expansion address/control buffers, and RTC address driver.
SN74HCT245 PDF Expansion and RTC data-bus transceivers.
SN74HCT32 PDF Logic OR gates.
SN74HCT574 PDF Debug-byte register and MIDI read-data hold register.
SN74HCT74 PDF Boot-overlay state, RTC request synchronizer, MFP clock divider, MIDI adapter state, and the VGA wait synchronizer.
CD74HC85 / SN74HC08 / SN74HC14 / SN74HC161 / SN74HC4060 / SN74HC74 HC85, HC08, HC14, HC161, HC4060, HC74 Power-control threshold comparison, gating, input conditioning, hold counter, oscillator/divider, and state storage.
CD74HCT164 PDF RTC, floppy, and VGA bus-cycle sequencers.
SN74HCT138 PDF Primary, system-register, and I/O-slot address decoding.
SN74F74 PDF 40 MHz to 10 MHz CPU clock divider, DRAM request and startup synchronizers, and the DRAM acknowledgement register.
SN74AHCT74 PDF Firmware ROM four-stage read-delay shift register.
SN74AHCT32 PDF Firmware ROM read-request and acknowledgement gating.
SN74LS148 PDF 8-line-to-3-line priority encoder for the /IPL inputs.
SN74LS174 PDF Two-stage /IPL synchronizer.
Epson SG-615PH PDF Installed 40 MHz C-grade CPU master oscillator.
14.31818 MHz oscillator PDF Through-hole 14.31818 MHz oscillator, one for the OPL3 and one for the CL-GD5428. The specification is given in opl3.html and vga.html. The linked Epson series datasheet is the reference part and the source of the output levels used in those checks; the ECS ECS-100AX-143 is an equivalent alternative.
DS1233-5 PDF Power-on reset supervisor and manual-reset sensing.
SN74LS14N PDF Two-stage Schmitt-trigger reset conditioner and MIDI input conditioner.
SN74LS07N PDF Open-collector CPU reset, halt, peripheral-reset, MIDI OUT, and MIDI THRU drivers.